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Toward Architecting and Designing Novel Computers

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Advances in Computer Systems Architecture (ACSAC 2003)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2823))

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Abstract

Recent CMOS technology faces challenging difficulties toward architecting and designing new computers. In the near future, chips will form a logic-sea, consisting of an immense number of gates and a very large amount of wires. This outstanding increase in chip density will require a drastic change in the building of computers, requiring novel microprocessors to be architected and designed. This paper introduces a novel architecture that considers the structural and behavioral constraints toward the implementation of future computers. A computation model that is strongly associated with this architecture is described with emphasis on the scheme of data processing. Finally, simple benchmarking illustrates the correctness of this architectural approach.

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References

  1. Lima, C.D., Sano, K., Kobayashi, H., Nakamura, T., Flynn, M.J.: A technology-scalable multithreaded architecture. In: Proc. of the 13th Symp. on Computer Architecture and High Performance Computing, pp. 82–89 (2001)

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© 2003 Springer-Verlag Berlin Heidelberg

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Nakamura, T. (2003). Toward Architecting and Designing Novel Computers. In: Omondi, A., Sedukhin, S. (eds) Advances in Computer Systems Architecture. ACSAC 2003. Lecture Notes in Computer Science, vol 2823. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39864-6_2

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  • DOI: https://doi.org/10.1007/978-3-540-39864-6_2

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-20122-9

  • Online ISBN: 978-3-540-39864-6

  • eBook Packages: Springer Book Archive

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