Abstract
This paper proposes an instruction-level parallel (ILP) processor with architecture reconfigurability. The processor can employ the optimal architecture to applications without loosing generality. Instruction-level parallelism is achieved by expanding the number of PUs depending on its load. Required features of reconfigurable hardware devices for such processors are discussed and the plastic cell architecture (PCA) is chosen as a target device for implementation of the ILP processor. Performance with reconfiguration overhead is measured and evaluated.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Wu, Y., Racvic, R., Chen, L.-L., Miao, C.-C., Chrysos, G., Fang, J.: Compiler Managed Micro-cache Bypassing for High Performance EPIC Processors. In: Int. Sym. on Micro architecture (Micro-35), pp. 134–145 (2002)
Hsu, S.-K., Lu, S.-L., Lai, S.-C., Krishnamurthy, R., Lai, K.: Dynamic Addressing Memory Arrays with Physical Locaity. In: Int. Sym. on Micro architecture (Micro-35), pp. 161–170 (2002)
Borns, J., Gaudiot, J.-L.: SMT Layout Overhead and Scalability. IEEE Trans. on Prallel, and Distributed Systems 13(2), 142–155 (2002)
Nakane, Y., Nagami, K., Shiozawa, T., Imligy, N., Nagoya, A., Oguri, K.: Runtime Resource Management for the Dynamically Self-Reconfigurable Architecture PCA. In: Proc. on ERSA 2001, pp. 67–72 (2001)
Smith, J.E.: Instruction-Level Distributed Processing. IEEE Computer, 59–65 (April 2001)
Ito, H., Oguri, K., Konishi, R., Nakada, H.: PCA Chip: Asynchronous Design of Dynamically Reconfigurable Logic LSI. Technical Report of IEICE, CPSY99-92, pp. 65–72 (1999) (in Japanese)
Ito, H., Konishi, R., Nakada, H., Oguri, K.: Dynamically Reconfigurable Logic LSI - PCA-1. Technical Report of IEICE, pp. 9–16, ED2000-111 (2000) (in Japanese)
Shiozawa, T., Nagami, K., Imlig, N., Konishi, R.: Applications and Design Environment for PCA. NTT Group’s Research and Development Activities 49(9), 527–536 (2000) (in Japanese)
Imlig, N., Shiozawa, T., Nagami, K., Oguri, K.: Communicating Logic: Digital Circuit Compilation for the PCA Architecture. In: DA Symposium 1999, pp. 101–106 (1999)
Ichikawa, M., Ono, K., Okuyama, Y., Kuroda, K.: A Reconfigurable and Stream-Oriented Vector Processor for Plastic Cell Architecture. In: Proc. 19th PERTHENON Workshop, pp. 3–12 (2001) (in Japanese)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Ito, T., Ono, K., Ichikawa, M., Okuyama, Y., Kuroda, K. (2003). Reconfigurable Instruction-Level Parallel Processor Architecture. In: Omondi, A., Sedukhin, S. (eds) Advances in Computer Systems Architecture. ACSAC 2003. Lecture Notes in Computer Science, vol 2823. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39864-6_17
Download citation
DOI: https://doi.org/10.1007/978-3-540-39864-6_17
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20122-9
Online ISBN: 978-3-540-39864-6
eBook Packages: Springer Book Archive