Abstract
Very Long Instruction Word (VLIW) architectures exploit instruction level parallelism (ILP) with the help of the compiler to achieve higher instruction throughput with minimal hardware. However, control and data dependencies between operations limit the available ILP, which not only hinders the scalability of VLIW architectures, but also result in code size expansion. Although speculation and predicated execution mitigate ILP limitations due to control dependencies to a certain extent, they increase hardware cost and exacerbate code size expansion.
Simultaneous multistreaming (SMS) can significantly improve operation throughput by allowing interleaved execution of operations from multiple instruction streams. In this paper we study SMS for VLIW architectures and quantify the benefits associated with it using a case study of the MPEG-2 video decoder. We also propose the notion of virtual resources for VLIW architectures, which decouple architectural resources (resources exposed to the compiler) from the microarchitectural resources, to limit code size expansion. Our results for a VLIW architecture demonstrate that: (1) SMS delivers much higher throughput than that achieved by speculation and predicated execution, (2) the increase in performance due to the addition of speculation and predicated execution support over SMS averages around 12%. The minor increase in performance might not warrant the additional hardware complexity involved, and (3) the notion of virtual resources is very effective in reducing no-operations (NOPs) and consequently reduce code size with little or no impact on performance.
This work is partially supported by a research grant from STMicroelectronics.
M.N.V. Satya Kiran: Satya Kiran is currently at the Indian Institute of Technology, New Delhi, India.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
The Trimaran Compiler Infrastructure, http://www.trimaran.org
Tullsen, D.M., Eggers, S.J., Emer, J.S., Levy, H.M., Lo, J.L., Stamm, R.L.: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. In: 23rd Annual International Symposium on Computer Architecture (May 1996)
Kathail, V., Schlansker, M.S., Ramakrishna Rau, B.: HPL-PD Architecture Specification: Version 1.1. Technical report HPL-93-80, HP Laboratories (February 2000)
Gyllenhaal, J.C., Hwu, W.W., Ramakrishna Rau, B.: HMDES Version 2.0 Specification. Technical Report, IMPACT-96-3
Jacome, M.F., de Veciana, G.: Design Challenges for New Application-Specific Processors. In: IEEE Design & Test of Computers (April-June 2000)
Hwu, W.W., Mahlke, S.A., et al.: The Superblock: An Effective technique for VLIW and Superscalar Compilation. The Journal of Supercomputing, 224–233 (May 1993)
Mahlke, S.A., Lin, D.C., Chen, W.Y., Hank, R.E., Bringmann, R.A.: Effective Compiler Support for Predicated Execution Using the Hyperblock. In: 27th International Symposium on Microarchitecture, November 1994, pp. 217–227 (1994)
Edler, J., Hill, M.: Dinero IV Trace-Driven Uniprocessor Cache Simulator, http://www.neci.nj.nec.com/homepages/edler/d4
Hwu, W.W., et al.: The IMPACT project, http://www.crhc.uiuc.edu/IMPACT
Aditya, S., Kathail, V., Rau, B.R.: Elcor’s machine description system: version 3.0. Technical Report HPL-98-128 (R.1), HP Laboratories (October 1998)
Schlansker, M.S., Ramakrishna Rau, B.: EPIC: An Architecture for Instruction-Level Parallel Processors. Technical Report HP-1999-111, HP Laboratories (February 2000)
Lee, C., Potkonjak, M., et al.: MediaBench: A Tool for Evaluating and Synthesising Multimedia and Communication Systems. In: 30th International Symposium on Microarchitecture, December 1997, pp. 330–335 (1997)
Bringmann, R.A., Mahlke, S.A., Hwu, W.-M.: A Study of the Effects of Compiler-Controlled Speculation on Instruction and Data Caches. In: Proceeding of the 28th Annual International Conference on System Sciences (January 1995)
Palacharla, S., Jouppi, N.P., Smith, J.E.: Complexity-Effective Superscalar Processors. In: 24th International Symposium on Computer Architecture, June 1997, pp. 206–218 (1997)
Texas Instruments TMS320C62x processor, http://www-k.ext.ti.com/sc/technical-support/tools/dsp/ftp/c62x.htm
Schlansker, M.S., Ramakrishna Rau, B., Mahlke, S., et al.: Acheiving High Levels of Instruction-Level Parallelism with Reduced Hardware Complexity. Technical Report HPL-96-120, HP Laboratories (November 1994)
Tullsen, D.M., Eggers, S.J., Levy, H.M.: Simultaneous Multithreading: Maximising on-chip Parallelism. In: 22nd AnnualInternational Symposium on Computer Architecture, June 1995, pp. 392–403 (1995)
Ozer, E., Conte, T.M., Sharma, S.: Weld: A Multithreading Technique Towards Latency-Tolerant VLIW Processors. In: 8th International Conference on High Performance Computing (December 2001)
Fritts, J., Wolfe, W.: Evaluation of Static and Dynamic Scheduling for Media Processors. In: MICRO-33 MP-DSP2 Workshop. ACM, New York (2000)
Prasadh, R.G., Wu, C.L.: A Benchmark Evaluation of a Multithreaded RISC Processor Architecture. In: International Conference on Parallel Processing, August 1991, pp. I:84–91 (1991)
Keckler, S.W., Dally, W.J.: Processor Coupling: Integrating Compile-time and Run-time Scheduling for Parallelism. In: 19th International Symposium on Computer Architecture (December 1995)
Partridge, R.: Cray Launches X1 for Extreme Supercomputing. Technology Trends, D.H. Brown Associates (November 2002)
The Berkeley Multimedia Research Center, http://bmrc.berkeley.edu/
Aho, A.V., Sethi, R., Ullman, J.D.: Compilers: Principles, Techniques and Tools. Pearson Education Pte. Ltd., London (2001)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Rao, H.P., Nandy, S.K., Kiran, M.N.V.S. (2003). Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures. In: Omondi, A., Sedukhin, S. (eds) Advances in Computer Systems Architecture. ACSAC 2003. Lecture Notes in Computer Science, vol 2823. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39864-6_14
Download citation
DOI: https://doi.org/10.1007/978-3-540-39864-6_14
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20122-9
Online ISBN: 978-3-540-39864-6
eBook Packages: Springer Book Archive