A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates
In this work we propose a compact analytical model to compute the crosstalk induced delay from a charge-based propagation delay model for submicronic CMOS gates. Crosstalk delay is described as an additional charge to be transferred through the pMOS (nMOS) network of the gate driving the victim node during its rising (falling) output transition. The model accounts for time skew between the victim and aggressor input transitions and includes submicronic effects. It provides an intuitive description of crosstalk delay showing very good agreement with HSPICE simulations for a 0.18μm technology.
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