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State Encoding for Low-Power FSMs in FPGA

  • Luis Mengibar
  • Luis Entrena
  • Michael G Lorenz
  • Raúl Sánchez-Reillo
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)

Abstract

In this paper, we address the problem of state encoding of FPGA-based Finite State Machines (FSMs) for low power dissipation. Recent work on this topic [1] shows that binary encoding produces best results for small FSMs (up to 8 states) while one-hot encoding produces best results for large FSMs (over 16 states). Departing from these results, we analyze other encoding alternatives that specifically take into account state transition probabilities. More precisely, we consider minimal-bit minimal Hamming distance encoding, zero-one-hot encoding and a partitioned encoding that uses a combination of both minimal-bit encoding and zero-one-hot encoding. Experimental results demonstrate that the proposed encoding techniques usually produce better results than the binary or one-hot encodings. Savings up to 60% can be obtained in the dynamic power dissipation by using the proposed encoding techniques.

Keywords

Power Dissipation Finite State Machine Switching Activity State Transition Probability State Encode 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Luis Mengibar
    • 1
  • Luis Entrena
    • 1
  • Michael G Lorenz
    • 1
  • Raúl Sánchez-Reillo
    • 1
  1. 1.Electronic Technology DepartmentUniversidad Carlos III de MadridSpain

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