State Encoding for Low-Power FSMs in FPGA

  • Luis Mengibar
  • Luis Entrena
  • Michael G Lorenz
  • Raúl Sánchez-Reillo
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)


In this paper, we address the problem of state encoding of FPGA-based Finite State Machines (FSMs) for low power dissipation. Recent work on this topic [1] shows that binary encoding produces best results for small FSMs (up to 8 states) while one-hot encoding produces best results for large FSMs (over 16 states). Departing from these results, we analyze other encoding alternatives that specifically take into account state transition probabilities. More precisely, we consider minimal-bit minimal Hamming distance encoding, zero-one-hot encoding and a partitioned encoding that uses a combination of both minimal-bit encoding and zero-one-hot encoding. Experimental results demonstrate that the proposed encoding techniques usually produce better results than the binary or one-hot encodings. Savings up to 60% can be obtained in the dynamic power dissipation by using the proposed encoding techniques.


Power Dissipation Finite State Machine Switching Activity State Transition Probability State Encode 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Sutter, G., Teodorovich, E., López-Buedo, S., Boemo, E.: Low-Power FSMs in FPGA: Encoding Alternatives. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds.) PATMOS 2002. LNCS, vol. 2451, pp. 459–467. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  2. 2.
    FPGA Compiler II / FPGA Express VHDL Reference Manual v. 1999.05. Synopsys Inc. (1999)Google Scholar
  3. 3.
    Xilinx Software Manual, Synthesis and Simulation Design Guide: Encoding State. Xilinx Inc. (2000)Google Scholar
  4. 4.
    Benini, L., De Micheli, G.: State Assignment for Low Power Dissipation. IEEE Journal of Solid State Circuits 30(3) (March 1995)Google Scholar
  5. 5.
    Tsui, C.-Y., Pedram, M., Despain, A.: Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs. In: Proc. Design Automation Conf., pp. 18–23 (1994)Google Scholar
  6. 6.
    Villa, T., Sangiovanni-Vincentelli, A.: NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Optimizations. IEEE Transactions on computer Aided Design 9(9), 905–924 (1990)CrossRefGoogle Scholar
  7. 7.
    Devadas, S., Ma, H., Newton, A.R., Sangiovanni-Vincentelli, A.: MUSTANG: State Assignment of Finite State MachinesTargeting Multi level Logic Implementations. IEEE Transactions on Computer Aided Design 7(12) (December 1990)Google Scholar
  8. 8.
    Lin, B., Newton, A.R.: Synthesis of Multiple Level Logic from Simbolic High-Level Description Languages. In: Proc. of International Conf. VLSI, Agosto 1996, pp. 187–196 (1996)Google Scholar
  9. 9.
    Chen, D.-S., Sharrafzadeh, M., Yeap, G.: State Encoding of Finite State Machines for Low Power Design. In: IEEE International Symposium on Circuits and Systems ISCAS 1995, vol. 3, pp. 2309–2312 (1995)Google Scholar
  10. 10.
    Nöth, W., Kolla, R.: Spanning Tree Based State Encodin for low power Dissipation. In: Proc. Design Aut. and Test in Europe DATE 1999, March 1999, pp. 168–174 (1999)Google Scholar
  11. 11.
    Wu, X., Pedram, M., Wang, L.: Multi-code state assignment for low power design. IEEE Proc. Circuits, Devices and Systems 147(5), 271–275 (2000)CrossRefGoogle Scholar
  12. 12.
    Martínez, M., Avedillo, M.J., Quintana, J.M., Huertas, J.L.: A flexible state assignment algorithm for low power implementations. In: Proc. Design of Circuits and Integrated Systems Conf., November 2001, pp. 154–159 (2001)Google Scholar
  13. 13.
    Koegst, M., Franke, G., Rulke, S.T., Feske, K.: A strategy for low power FSM-Design Using multicriteria approach. In: PATMOS 1997, pp. 323–329 (1997)Google Scholar
  14. 14.
    McElvain, K.: LGSynth93 Benchmark Set: Version 4.0 (1993)Google Scholar
  15. 15.
    Sentovich, E., Singh, K., Lavagno, L., Moon, C., Murgai, R., Saldanha, A., Stephan, P., Brayton, R., Sangiovanni-Vincentelli, A.: SIS: A System for Sequential Circuit Synthesis. Tech. Report Mem. No UCB/ERL M92/41, Univ. California Berkeley (1992)Google Scholar
  16. 16.
    Modelsim SE/EE Plus 5.4E. User‘s manual, V. 5.4. Model Technology Incorporated (August 2000)Google Scholar
  17. 17.
    Xilinx Foundation 4.1i tools,
  18. 18.
    Xpower, Xpower Tutorial FPGA Design, Xpower (V1.0), Xilinx Inc (May 11, 2001)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Luis Mengibar
    • 1
  • Luis Entrena
    • 1
  • Michael G Lorenz
    • 1
  • Raúl Sánchez-Reillo
    • 1
  1. 1.Electronic Technology DepartmentUniversidad Carlos III de MadridSpain

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