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Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms

  • K. Tatas
  • K. Siozios
  • D. Soudris
  • K. Masselos
  • K. Potamianos
  • S. Blionas
  • A. Thanailakis
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)

Abstract

A methodology for the power-efficient implementation of multimedia kernels based on reconfigurable hardware (FPGA) is introduced. The methodology combines various types of algorithmic transformations and high-level memory hierarchy exploration with register-transfer level design and implementation. An FPGA with an external memory was used for obtaining experimental results which prove the viability of the methodology. Comparisons among implementations with and without this optimization, prove that great power efficiency is achieved.

Keywords

Motion Vector External Memory Full Search Memory Hierarchy Custom Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • K. Tatas
    • 1
  • K. Siozios
    • 1
  • D. Soudris
    • 1
  • K. Masselos
    • 2
  • K. Potamianos
    • 2
  • S. Blionas
    • 2
  • A. Thanailakis
    • 1
  1. 1.VLSI Design and Testing Center, Department of Electrical and Computer EngineeringDemocritus University of ThraceXanthiGreece
  2. 2.Intracom SA, Hellenic Telecommunications IndustryPeaniaGreece

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