Advertisement

Power-Aware Branch Predictor Update for High-Performance Processors

  • Amirali Baniasadi
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)

Abstract

We introduce Power-Aware Branch Predictor Update (PABU) as a power-efficient branch prediction technique for high performance processors. Our predictor reduces branch prediction energy consumption by eliminating unnecessary branch predictor updates. Our technique relies on information regarding past branch behavior to decide if additional predictor updates result in performance improvements. We avoid updating the predictor for branches where there is already enough information available to correctly predict their outcome. In this work we study energy and performance trade-offs for a subset of SPEC 2k benchmarks. We show that on the average and for an 8-way processor, our technique can reduce branch prediction energy consumption up to 80%compared to a 32k conventional combined branch predictor. This comes with a negligible impact on performance (0.6%max). We show that our technique, on the average, reduces the number of predictor updates by 83%.

Keywords

Power Dissipation Cache Line Predictor State Branch Prediction Branch Instruction 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Parikh, D., Skadron, K., Zhang, Y., Barcella, M., Stan, M.R.: Power Issues Related to Branch Prediction. In: Proc. Intl. Symposium on High-Performance Computer Architecture (February 2002)Google Scholar
  2. 2.
    Manne, S., Klauser, A., Grunwald, D.: Pipeline Gating: Speculation Control For Energy Reduction. In: Proc. Intl. Symposium on Computer Architecture (June 1998)Google Scholar
  3. 3.
    Grunwald, D., Klusser, A., Manne, S., Plezkun, A.: Confidence Estimation for Speculation Control. In: Proc. Intl. Symposium on Computer Architecture (June 1998)Google Scholar
  4. 4.
    Baniasadi, A., Moshovos, A.: Instruction Flow-Based Front-end Throttling for Power-Aware High-Performance Processors. In: Proc. ISLPED 2001 (August 2001)Google Scholar
  5. 5.
    Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A Framework for Architectural-Level Power Analysis and Optimization. In: Proc of the 27th Int’l Symp. on Computer Architecture (2000)Google Scholar
  6. 6.
    Baniasadi, A., Moshovos, A.: Branch Predictor Predcition a Power-Aware Branch Predcitor for High-Performance Processors. In: Proc. ICCD 2002 (September 2002)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Amirali Baniasadi
    • 1
  1. 1.Dept.of Electrical and Computer EngineeringUniversity of VictoriaCanada

Personalised recommendations