Energy Optimization of High-Performance Circuits
As technology scales, energy consumption is becoming an important issue in high-performance VLSI microprocessor designs. Often the critical path of these microprocessors is in the datapath of arithmetic units, resulting in high energy consumption along the datapath. We propose an optimization method that can achieve energy saving versus delay-based optimization at equal performance. It reveals that the source of energy saving lays in the balance of delay and energy consumption among different stages of a circuit. The energy saving is significant, 30%(50%. The results are confirmed with simulation, using Fujitsu’s 0.11μm, 1.2V CMOS technology.
Unable to display preview. Download preview PDF.
- 1.Oklobdzija, V.G., Zeydel, B., Dao, H.Q., Mathew, S., Krishnamurthy, R.: Energy-Delay Estimation for High-Performance Microprocessor VLSI Adders. In: Proceeding of the 16th Symposium on Computer Arithmetic (June 2003)Google Scholar
- 2.Harris, D., Sproull, R.F., Sutherland, I.E.: Logical Effort Designing Fast CMOS Circuits. Morgan Kaufmann Publishers, San Francisco (1999)Google Scholar
- 3.Stojanovic, V., Markovic, D., Nikolic, B., Horowitz, M.A., Brodersen, R.W.: Energy-Delay Tradeoffs in Combinational Logic Using Gate Sizing and Supply Voltage Optimization. In: Proceedings of the 28th European Solid-State Circuits Conference, ESSCIRC 2002, Florence, Italy, September 24–26, pp. 211–214 (2002)Google Scholar
- 4.Brodersen, R.W., Horowitz, M.A., Markovic, D., Nikolic, B., Stojanovic, V.: Methods for True Power Minimization. In: International Conference on Computer-Aided Design, ICCAD-2002, Digest of Technical Papers, San Jose, CA, November 10–14, pp. 35–42 (2002)Google Scholar
- 5.Zyuban, V., Strenski, P.: Unified Methodology for Resolving Power-Performance Tradeoffs at the Microachitectural and Circuit Levels. In: IEEE Symposium on Low Power Electronics and Design (2002)Google Scholar
- 6.Zyuban, V.V., Kogge, P.M.: Inherently Lower-Power High-Performance Superscalar Architectures. In: IEEE Symposium on Low Power Electronics and Desing (2001)Google Scholar
- 7.Dao, H., Oklobdzija, V.G.: Performance Comparison of VLSI Adders Using Logical Effort. In: 12th International Workshop on Power And Timing Modeling,Optimization and Simulation, Sevilla, SPAIN, September 11–13 (2002)Google Scholar
- 9.Han, T., Carlson, D.A., Levitan, S.P.: VLSI Design of High-Speed Low-Area Addition Circuitry. In: Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 418–422 (1987)Google Scholar