Abstract
A 3.3V, 0.8 mW programmable Numerical Controlled oscillator Oscillator (NCO) core is designed in 0.6 micron CMOS process and its prototype design is mapped on an Altera MAX9400 CPLD. This architecture is suitable for digital wireless transceivers that use different bands for transmit and receive modes, such as GSM and DECT. Linearity and phase noise of the NCO is analyzed. Thermal drift and power supply level sensitivity is characterized. This architecture can be used for higher frequencies using faster FPGA devices or by implementing it on an advanced deep-submicron process.
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© 2003 Springer-Verlag Berlin Heidelberg
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Abdollahi, S.R., Bakkaloglu, B., Hosseini, S.K. (2003). A Fully Digital Numerical-Controlled-Oscillator. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_45
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DOI: https://doi.org/10.1007/978-3-540-39762-5_45
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20074-1
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