Instruction Level Energy Modeling for Pipelined Processors
A new method for creating instruction level energy models for pipelined processors is introduced. This method is based on measuring the instantaneous current drawn by the processor during the execution of the instructions. An appropriate instrumentation set up was established for this purpose. According to the proposed method the energy costs (base and inter-instruction costs) are modeled in relation to a reference instruction (e.g. NOP). These costs incorporate inter-cycle energy components, which cancel each other when they are summed to produce the energy consumption of a program resulting in estimates with high accuracy. This is confirmed by the results. Also the dependencies of the energy consumption on the instruction parameters (e.g. operands, addresses) are studied and modeled in an efficient way.
KeywordsClock Cycle Very Large Scale Inte Pipeline Stage Instantaneous Current Base Cost
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- 3.Lee, M.T.-C., Tiwari, V., Malik, S., Fujita, M.: Power Analysis and Minimization Tehniques for Embedded DSP Software. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 123–135 (1997)Google Scholar
- 4.Tiwari, V., Lee, T.C.: Power Analysis of a 32-bit Embedded Microcontroller. VLSI Design Journal 7(3) (1998)Google Scholar
- 5.SOFLOPO, Low Power Development for Embedded Applications, ESPRIT project: Deliverable 2.2: Physical measurements. By Thanos Stouraitis, University of Patras (December 1998)Google Scholar
- 6.Steinke, S., Knauer, M., Wehmeyer, L., Marwedel, P.: An Accurate and Fine Grain Instruction- Level Energy Model supporting Software Optimizations. In: Int. Workshop on Power and Timing Modeling, Optimization and Simulation, Yverdon-les-bains, Switzerland (2001)Google Scholar
- 7.Russell, J.T., Jacome, M.F.: Software Power Estimation and Optimization for High Performance, 32-bit Embedded Processors. In: Int. Conf. On Computer Design (1998)Google Scholar
- 9.Lee, S., Ermedahl, A., Min, S.-L., Chang, N.: An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors. In: ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems (2001)Google Scholar
- 10.Nikolaidis, S., Kavvadias, N., Neofotistos, P., Kosmatopoulos, K., Laopoulos, T., Bisdounis, L.: Instrumentation set-up for Instruction Level Power Modeling. In: Int. Workshop on Power and Timing Modeling, Optimization and Simulation, Seville, Spain (September 2002)Google Scholar
- 11.Nikolaidis, S., Kavvadias, N., Neofotistos, P.: Instruction level power measurements and analysis. IST-2000-30093/EASY Project, Deliverable (September 15, 2002), http://easy.intranet.gr
- 12.Nikolaidis, S., Kavvadias, N., Neofotistos, P.: Instruction level power models for embedded processors. IST-2000-30093/EASY Project, Deliv. 21 (December 2002), http://easy.intranet.gr