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High-Level Area and Current Estimation

  • Fei Li
  • Lei He
  • Joe Basile
  • Rakesh J. Patel
  • Hema Ramamurthy
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)

Abstract

Reducing the ever-growing leakage current is critical to high performance and power efficient designs. We present an in-depth study of high-level leakage modeling and reduction in the context of a full custom design environment. We propose a methodology to estimate the circuit area, minimum and maximum leakage current, and maximum power-up current, introduced by leakage reduction using sleep transistor insertion, for any given logic function. We build novel estimation metrics based on logic synthesis and gate level analysis using only a small number of typical circuits, but no further logic synthesis and gate level analysis are needed during our estimation. Compared to time-consuming logic synthesis and gate level analysis, the average errors for circuits from a leading industrial design project are 23.59% for area, 21.44% for maximum power-up current. In contrast, estimation based on quick synthesis leads to 11x area difference in gate count for an 8bit adder.

Keywords

Output Probability Spice Simulation Gate Count Logic Synthesis Prime Implicants 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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    Krstic, A., Cheng, K.-T.: Vector generation for maximum instantaneous current through supply lines for CMOS circuits. In: Proc. Design Automation Conf., June 1997, pp. 383–388 (1997)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Fei Li
    • 1
  • Lei He
    • 1
  • Joe Basile
    • 2
  • Rakesh J. Patel
    • 2
  • Hema Ramamurthy
    • 2
  1. 1.EE DepartmentUniversity of CaliforniaLos Angeles
  2. 2.Intel CorporationSan Jose

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