A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems

  • Gianluca Palermo
  • Cristina Silvano
  • Vittorio Zaccaria
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)


The evaluation of the best system-level architecture in terms of energy and performance is of mainly importance for a broad range of embedded SOC platforms. In this paper, we address the problem of the efficient exploration of the architectural design space for parameterized microprocessor-based systems. The architectural design space is multi-objective, so our aim is to find all the Pareto-optimal configurations representing the best power-performance design trade-offs by varying the architectural parameters of the target system. In particular, the paper presents a Design Space Exploration (DSE) framework tuned to efficiently derive Pareto-optimal curves. The main characteristics of the proposed framework consist of its flexibility and modularity, mainly in terms of target architecture, related system-level executable models, exploration algorithms and system-level metrics. The analysis of the proposed framework has been carried out for a parameterized superscalar architecture executing a selected set of benchmarks. The reported results have shown a reduction of the simulation time of up to three orders of magnitude with respect to the full search strategy, while maintaining a good level of accuracy (under 4% on average).


Design Space Very Large Scale Integration Design Space Exploration Pareto Point Target Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Su, C.L., Despain, A.M.: Cache design trade-offs for power and performance optimization: A case study. In: ISLPED-1995: ACM/IEEE Int. Symposium on Low Power Electronics and Design (1995)Google Scholar
  2. 2.
    Li, Y., Henkel, J.: A framework for estimating and minimizing energy dissipation of embedded hw/sw systems. In: DAC-35: ACM/IEEE Design Automation Conference (June 1998)Google Scholar
  3. 3.
    Kin, J.K., Gupta, M., Mangione-Smith, W.H.: Filtering Memory References to Increase Energy Efficiency. IEEE Trans. on Computers 49(1) (January 2000)Google Scholar
  4. 4.
    Conte, T.M., Menezes, K.N., Sathaye, S.W., Toburen, M.C.: System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. IEEE Trans. on Very Large Scale Integration (VLSI) Systems 8(2), 129–137 (2000)CrossRefGoogle Scholar
  5. 5.
    Burger, D., Austin, T.M., Bennett, S.: Evaluating future microprocessors: The simplescalar tool set. Technical Report CS-TR-1996-1308, University of Wisconsin (1996)Google Scholar
  6. 6.
    Brooks, D., Tiwari, V., Martonosi, M.: Wattch: a framework for architectural-level power analysis and optimizations. In: Proceedings ISCA 2000, pp. 83–94 (2000)Google Scholar
  7. 7.
    Bellas, N., Hajj, I.N., Polychronopoulos, D., Stamoulis, G.: Architectural and compiler techniques for energy reduction in high-performance microprocessors. IEEE Transactions on Very Large Scale of Integration (VLSI) Systems 8(3) (June 2000)Google Scholar
  8. 8.
    Vijaykrishnan, N., Kandemir, M., Irwin, M.J., Kim, H.S., Ye, W.: Energy-driven integrated hardware-software optimizations using simple power. In: ISCA 2000: 2000 International Symposium on Computer Architecture, Vancouver BC, Canada (June 2000)Google Scholar
  9. 9.
    Givargis, T.D., Vahid, F.: Platune: a tuning framework for system-on-achip platforms. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21(11), 1317–1327 (2002)CrossRefGoogle Scholar
  10. 10.
    Palesi, M., Givargis, T.: Multi-objective design space exploration using genetic lgorithms. In: Proceedings of the Tenth International Symposium on Hardware/ Software Codesign 2002, CODES 2002 (May 6–8, 2002)Google Scholar
  11. 11.
    Gajski, D., Dutt, N., Wu, A., Lin, S.: High-Level Synthesis, Introduction to Chip and System Design. Kluwer Academic Publishers, Dordrecht (1994)Google Scholar
  12. 12.
    Keutzer, K., Malik, S., Newton, A.R., Rabaey, J., Sangiovanni-Vincentelli, A.: System level design: Orthogonolization of concerns and platform-based design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19(12), 1523–1543 (2000)CrossRefGoogle Scholar
  13. 13.
    Aho, A., Hopcroft, J., Ullman, J.: Data Structures and Algorithms. Addison-Wesley, Reading (1983)zbMATHGoogle Scholar
  14. 14.
    Zhigljavsky, A.A.: Theory of global random search, vol. 65. Kluwer Academic publishers Group, Dordrecht (1991)Google Scholar
  15. 15.
    Jaszkiewicz, A., Czyak, P.: Pareto simulated annealing - a metaheuristic technique for multiple-objective combinatorial optimisation. Journal of Multi-Criteria Decision Analysis (7), 34–47 (1998)zbMATHCrossRefGoogle Scholar
  16. 16.
    Battiti, R., Tecchiolli, G.: The reactive tabu search. ORSA Journal on Computing 6(2), 126–140 (1994)zbMATHGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Gianluca Palermo
    • 1
  • Cristina Silvano
    • 1
  • Vittorio Zaccaria
    • 2
  1. 1.DEIPolitecnico di MilanoMilanoItaly
  2. 2.STMicroelectronicsAgrate BrianzaItaly

Personalised recommendations