Low Voltage, Double-Edge-Triggered Flip Flop

  • Pradeep Varma
  • Ashutosh Chakraborty
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)


Double-edge-triggered flip flops (DETFFs) are recognized as power-saving flip flops. We study the same from a low voltage perspective [1-1.5V]. We combine a medium-to-high voltage, plain-MOS-style DETFF technique with a clock-skew technique to derive a new DETFF that is suited to low voltages. Speedwise, our result outperforms existing static DETFFs convincingly in the low voltage range. Powerwise, our flip flop beats others for dynamic input in the lower half of the same range. The dynamic counterpart of our static circuit also shows similar power superiority at low voltages.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Afghahi, M., Yuan, J.: Double Edge-Triggered D-Flip-Flops for High-Speed CMOS Circuits. IEEE J. Solid-State Circuits 26(8), 1168–1170 (1991)CrossRefGoogle Scholar
  2. 2.
    Blair, G.M.: Low-power double-edge triggered flipflop. Electronics Letters 33(10), 845–847 (1997)CrossRefGoogle Scholar
  3. 3.
    Gago, A., Escano, R., Hidalgo, J.A.: Reduced Implementation of D-Type DET Flip-Flops. IEEE J. Solid-State Circuits 28(3), 400–402 (1993)CrossRefGoogle Scholar
  4. 4.
    Hossain, R., Wronski, L.D., Albicki, A.: Low Power Design Using Double Edge Triggered Flip-Flops. IEEE Trans. VLSI 2(2), 261–265 (1994)CrossRefGoogle Scholar
  5. 5.
    Kang, S.M.: Accurate simulation of power dissipation in VLSI circuits. IEEE J. Solid-State Circuits SC-21(5), 889–891 (1986)CrossRefGoogle Scholar
  6. 6.
    Lu, S., Ercegovac, M.: A Novel CMOS Implementation of Double-Edge-Triggered Flip-Flops. IEEE J. Solid-State Circuits 25(4), 1008–1010 (1990)CrossRefGoogle Scholar
  7. 7.
    Unger, S.: Double edge-triggered flip-flops. IEEE Trans. Computers C-30(6), 447–451 (1981)CrossRefGoogle Scholar
  8. 8.
    Varma, P., Panwar, B.S., Chakraborty, A., Kapoor, D.: A MOS Approach to CMOS DET Flip-Flop Design. IEEE Trans. Circuits and Systems – I 49(7), 1013–1016 (2002)CrossRefGoogle Scholar
  9. 9.
    Varma, P., Ramganesh, K.N.: Skewing Clock to Decide Races – Double-Edge- Triggered Flip Flop. Electronics Letters 37(25), 1506–1507 (2001)CrossRefGoogle Scholar
  10. 10.
    Yun, K.Y., Beerel, P., Arceo, J.: High-performance two-phase micropipeline building blocks: double edge-triggered latches and burst-mode select and toggle circuits. IEE Proc.-Circuits Devices Syst. 143(5), 282–288 (1996)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Pradeep Varma
    • 1
  • Ashutosh Chakraborty
    • 1
  1. 1.IBM India Research Laboratory, Block 1Indian Institute of TechnologyHauz Khas, New DelhiIndia

Personalised recommendations