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Low Voltage, Double-Edge-Triggered Flip Flop

  • Pradeep Varma
  • Ashutosh Chakraborty
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)

Abstract

Double-edge-triggered flip flops (DETFFs) are recognized as power-saving flip flops. We study the same from a low voltage perspective [1-1.5V]. We combine a medium-to-high voltage, plain-MOS-style DETFF technique with a clock-skew technique to derive a new DETFF that is suited to low voltages. Speedwise, our result outperforms existing static DETFFs convincingly in the low voltage range. Powerwise, our flip flop beats others for dynamic input in the lower half of the same range. The dynamic counterpart of our static circuit also shows similar power superiority at low voltages.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Pradeep Varma
    • 1
  • Ashutosh Chakraborty
    • 1
  1. 1.IBM India Research Laboratory, Block 1Indian Institute of TechnologyHauz Khas, New DelhiIndia

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