Low Voltage, Double-Edge-Triggered Flip Flop
Double-edge-triggered flip flops (DETFFs) are recognized as power-saving flip flops. We study the same from a low voltage perspective [1-1.5V]. We combine a medium-to-high voltage, plain-MOS-style DETFF technique with a clock-skew technique to derive a new DETFF that is suited to low voltages. Speedwise, our result outperforms existing static DETFFs convincingly in the low voltage range. Powerwise, our flip flop beats others for dynamic input in the lower half of the same range. The dynamic counterpart of our static circuit also shows similar power superiority at low voltages.
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