Abstract
Power estimation at the Register-Transfer level is usually narrowed down to the problem of building accurate power models for the RTL (synthetic) operators. In this work we show that, when RTL power estimation is integrated into a realistic design flow, other types of primitives need to be accurately modeled. In particular, we show that most of the RTL functionality is realized by sparse logic elements.
We thus propose statistical power models for these primitives, that we have validated on a set of industrial benchmarks.
This work is supported, in part, by the EC under contract IST-2001-30125 ”POET”
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Bruno, M., Macii, A., Poncino, M. (2003). A Statistical Power Model for Non-synthetic RTL Operators. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_27
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DOI: https://doi.org/10.1007/978-3-540-39762-5_27
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20074-1
Online ISBN: 978-3-540-39762-5
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