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A Statistical Power Model for Non-synthetic RTL Operators

  • Maurizio Bruno
  • Alberto Macii
  • Massimo Poncino
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)

Abstract

Power estimation at the Register-Transfer level is usually narrowed down to the problem of building accurate power models for the RTL (synthetic) operators. In this work we show that, when RTL power estimation is integrated into a realistic design flow, other types of primitives need to be accurately modeled. In particular, we show that most of the RTL functionality is realized by sparse logic elements.

We thus propose statistical power models for these primitives, that we have validated on a set of industrial benchmarks.

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References

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    Gajski, D.D., Dutt, N.D., Wu, A.C.-H., Lin, S.Y.-L.: High-Level Synthesis Introduction to Chip and System Design. Kluwer Academic Publishers, Dordrecht (1992)Google Scholar
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    Bogliolo, A., Colonescu, I., Corgnati, R., Macii, E., Poncino, M.: An RTL Power Estimation Tool with On-Line Model Building Capabilities. In: PATMOS 2001, Yverdonles- bains, Switzerland (September 2001)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Maurizio Bruno
    • 1
  • Alberto Macii
    • 2
  • Massimo Poncino
    • 3
  1. 1.BullDast s.r.l.TorinoITALY
  2. 2.Politecnico di TorinoTorinoITALY
  3. 3.Università di VeronaVeronaITALY

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