Advertisement

Statistical Power Estimation of Behavioral Descriptions

  • B. Arts
  • A. Bellu
  • L. Benini
  • N. van der Eng
  • M. Heijligers
  • E. Macii
  • A. Milia
  • R. Maro
  • H. Munk
  • F. Theeuwen
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)

Abstract

Power estimation of behavioral descriptions is a difficult task, as it entails inferring the hardware architecture on which the behavioral specification will be mapped through synthesis before the synthesis is actually performed. To cope with the uncertainties related to handling behavioral descriptions, we introduce the concept of statistical estimation, and we sketch how a prototype statistical power estimator has been implemented within a high-level design exploration framework (the AspeCts environment).

Keywords

Power Consumption Functional Unit Power Estimation Hardware Architecture Switching Activity 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Synopsys, Inc., Synopsys PowerCompiler, http://www.synopsys.com
  2. 2.
    Sequence Design, Inc., PowerTheater, http://www.sequencedesign.com
  3. 3.
    BullDAST s.r.l., PowerChecker, http://www.bulldast.com
  4. 4.
    San Martin, R., Knight, J.P.: Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level. In: DAC-32, pp. 42–47 (1995)Google Scholar
  5. 5.
    Kruse, L., et al.: Estimation of Lower and Upper Bounds on the Power Consumption from Scheduled Data Flow Graphs. IEEE TVLSI 9, 3–14 (2001)Google Scholar
  6. 6.
    Bruni, D., Bogliolo, A., Benini, L.: Statistical Design Space Exploration for Application-Specific Unit Synthesis. In: DAC-38, pp. 641–646 (2001)Google Scholar
  7. 7.
    Heijligers, M.J.M., Hogenhuis, A.: Analyzing Architectural AspeCts of Behavioral Descriptions. In: Conf. on Embedded System Design, pp. 239–250 (2000)Google Scholar
  8. 8.
    Wilton, S.J.E., Jouppi, N.P.: CACTI: An Enhanced Cache Access and Cycle Time Model. IEEE JSSC 31, 677–688 (1996)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • B. Arts
    • 1
  • A. Bellu
    • 2
  • L. Benini
    • 3
  • N. van der Eng
    • 1
  • M. Heijligers
    • 1
  • E. Macii
    • 2
  • A. Milia
    • 2
  • R. Maro
    • 2
  • H. Munk
    • 1
  • F. Theeuwen
    • 1
  1. 1.Philips Research LabsED&T/SynthesisEindhovenNL
  2. 2.Politecnico di Torino, DAUINTorinoI
  3. 3.Università di Bologna, DEISBolognaI

Personalised recommendations