Signal Integrity and Power Supply Network Analysis of Deep SubMicron Chips

  • Louis K. Scheffer
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)


In the recent past, chip designers were mainly worried about logical correctness, adherence to design rules, and chip timing. Neither the power supply network, nor the signal nets, needed to be analyzed in detail for analog effects or possible reliability problems.

However, in modern DSM chip technologies, these simplifications are no longer good enough. The power supply network, for example, must be designed from the beginning as opposed to added as an afterthought, and must take into account many other aspects of the chip, from the package in which it will be placed, to the detailed needs of the logic that composes the blocks.

Furthermore, reliability issues are even more worrying, for these cannot=

be found by testing when the chip is new – they develop over time and may cause a chip to fail in the field that worked perfectly well on the tester. Electromigration, wire self heat, and hot-electron effects fall into this category, affecting the power supply wires, the signal wires, and the gates respectively.

A new generation of tools has been developed to address these problems, both for power supply networks and signal nets. This paper and presentation will discuss the motivation, technology, and operation of these tools. The power supply analysis tools combine static and dynamic analysis to ensure that the quality of the delivered power is sufficiently high and that the supply network will be reliable over the life of the chip. In addition, since power supply voltage has a big effect on both timing and=

signal integrity, the power supply analysis tools must relay their findings to these other tools, and these other tools must correctly account for these variations.

The signal net analysis tools look at different analog effects. They look at changes in timing induced by changes in power supplies and the behavior of nearby nets. Furthermore, they examine the gates and wires for any potential reliability problems.

Finally, we will discuss some of the strategies employed by tools such as placement, routing, and synthesis, and how they attempt to avoid these problems in the first place.

Such a flow, combining both avoidance and accurate analysis, is necessary to allow both high productivity and adherence to the more complex constraints of DSM design.

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Louis K. Scheffer
    • 1
  1. 1.CadenceSan JoseUSA

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