Analysis of High-Speed Logic Families
In this paper, we compare the current de-facto standard high-speed family (self-resetting domino logic) with the most promising recently proposed ones: dynamic current mode logic, gate diffusion input logic and race logic architecture. For this purpose, we have used an 8-bit array multiplier in the 0.13 um TSMC CMOS process whose critical path is representative of many modern complex ICs. Each design adopts solely one logic style and it has been optimized with a standard industrial semi-custom flow. As metrics of comparison we have used speed and the energy (E), energy-per-time (ET) and energy-per-time-square (ET2) metrics. The comparison shows that self-resetting domino logic is the best choice when only speed is of concern, while dynamic current mode logic should be the preferred approach for all other cases. The other logic families failed to live up with their original promises of high-performance.
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