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Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders

  • João Leonardo Fragoso
  • Gilles Sicard
  • Marc Renaudin
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)

Abstract

This work describes generalized structures to design 1-of-M QDI (Quasi Delay-Insensitive) asynchronous adders. Those structures allow to design from simple ripple-carry adders to faster parallel-prefix adders. The proposed method is fully automated and integrated in TAST (TIMA Asynchronous Synthesis Tool) tools suite. This paper also demonstrates that the most widely used dual-rail encoding (binary representation in QDI circuits) is not the best solution for numbers’ representation in asynchronous circuits. In fact, according to the domain of values to be represented increasing the radix leads to parallel-prefix adders with lower area, delay and power consumption. Hence, this work enables the designer to optimize his/her design by choosing the appropriate 1-of-M number representation.

Keywords

Computation Tree Regular Layout Asynchronous Circuit Grey Node Output Wire 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • João Leonardo Fragoso
    • 1
  • Gilles Sicard
    • 1
  • Marc Renaudin
    • 1
  1. 1.TIMA Laboratory / CIS GroupGrenoble CedexFRANCE

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