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Power-Consumption Reduction in Asynchronous Circuits Using Delay Path Unequalization

  • Sonia López
  • Óscar Garnica
  • Ignacio Hidalgo
  • Juan Lanchares
  • Román Hermida
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)

Abstract

The goal of this paper is to present a new technique to reduce power-consumption in circuits with detection of computation completion (asynchronous circuits) by adding delay elements in paths of the circuit. The aim of these new elements is to decrease the number of switchings of those gates placed in the logic cone of the delay element due to the computation completion before those gates receive the new incoming values. We have studied this approach for a set of benchmarks (LGSynth95) and evaluated the trade-off between power-consumption reduction and performance degradation.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Sonia López
    • 1
  • Óscar Garnica
    • 1
  • Ignacio Hidalgo
    • 1
  • Juan Lanchares
    • 1
  • Román Hermida
    • 1
  1. 1.Departamento de Arquitectura de Computadores y AutomáticaUniversidad Complutense de MadridEspaña

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