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A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization

  • M. Addino
  • M. R. Casu
  • G. Masera
  • G. Piccinini
  • M. Zamboni
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)

Abstract

A method for SoC global interconnect characterization is presented. Buses are partitioned in blocks whose electrical characterization is done using reduced size primitives and extending the results to the original structure. The accuracy is measured on typical metrics like delays, crosstalk peaks and reabsorbing time. This work is the basis for an automatic evaluator of interconnect metrics to be used in SoC design space explorations and verification.

Keywords

Mutual Inductance Parameter Extraction Metal Line Border Line Coupling Length 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • M. Addino
    • 1
  • M. R. Casu
    • 1
  • G. Masera
    • 1
  • G. Piccinini
    • 1
  • M. Zamboni
    • 1
  1. 1.Politecnico di TorinoTorinoItaly

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