A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization
A method for SoC global interconnect characterization is presented. Buses are partitioned in blocks whose electrical characterization is done using reduced size primitives and extending the results to the original structure. The accuracy is measured on typical metrics like delays, crosstalk peaks and reabsorbing time. This work is the basis for an automatic evaluator of interconnect metrics to be used in SoC design space explorations and verification.
KeywordsMutual Inductance Parameter Extraction Metal Line Border Line Coupling Length
Unable to display preview. Download preview PDF.
- 3.Kleveland, B., et al.: High-Frequency Characterization of On-Chip Digital Inteconnects. IEEE JSSC 37(6), 716–725 (2002)Google Scholar
- 6.Avant! Corporation. Avant Star-HSPICE Manual Release, 4 (2000)Google Scholar
- 7.Davis, J.A.: A Hierarchy of Interconnects Limits and Opportunities for Gigascale Integration. PhD thesis, Georgia Institute of Technology (1999)Google Scholar