Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits

  • Jérôme Lescot
  • François J. R. Clément
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)


A tool to model interconnect parasitics in radio-frequency (RF) integrated circuits (RFICs) is presented. Accurate modeling is achieved by combining a detailed RLC wire model together with a distributed RC substrate model. Wire geometry is fractured to ensure accurate modeling of wave propagation as well as displacement current due to substrate losses. The wire model includes resistance and coupled capacitance together with self and mutual inductance. The necessity of including a distributed RC model of the substrate is stressed. RLC reduction at the end of parasitic extraction allows for fast simulation of the complete model. Accuracy and performance are demonstrated by comparing the values extracted by the tool against results from existing computer software as well as against silicon measurements.


Mutual Inductance Proximity Effect Spiral Inductor Wire Model Parasitic Extraction 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Hasegawa, H., Furukawa, M., Yanai, H.: Properties of Microstrip Line on Si-SiO2 System. IEEE Transactions on Microwave Theory and Techniques 19, 869–881 (1971)CrossRefGoogle Scholar
  2. 2.
    Sitaram, D., Zheng, Y., Shepard, K.L.: Implicit Treatment of Substrate and Power- Ground Losses in Return-Limited Inductance Extraction. In: Presented at International Conference on Computer Aided Design (2002)Google Scholar
  3. 3.
    Weeks, W.T., Wu, L.L., Allister, M.F.M., Singh, A.: Resistive and Inductive Skin Effect in Rectangular Conductors. IBM Journal of Research and Development 23, 652–660 (1979)CrossRefGoogle Scholar
  4. 4.
    Bächtold, M., Spasojevic, M., Lage, C., Ljung, P.B.: A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3D field solver. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19, 325–338 (2000)CrossRefGoogle Scholar
  5. 5.
    Ruehli, A.E.: Inductance Calculations in a Complex Integrated Circuit Environment. IBM Journal of Research and Development, 470–481 (1972)Google Scholar
  6. 6.
    Hoer, C., Love, C.: Exact Inductance Equations for Rectangular Conductors with Approximations to More Complicated Geometries. IBM Journal of Research of the National Bureau of Standards – Computer Engineering and Instrumentation 69C, 127–137 (1965)Google Scholar
  7. 7.
    Clément, F.J.R.: Computer Aided Analysis of Parasitic Substrate Coupling in Mixed Digital-Analog CMOS Integrated Circuits, Ph. D. thesis dissertation, EPFL, Lausanne (1995)Google Scholar
  8. 8.
    Carbon, E., Gharpurey, R., Miliozzi, P., Meyer, R.G., Sangiovanni-Vincentelli, A.L.: Substrate Noise Analysis and Optimization for IC Design. Kluwer Academic Publishers, Dordrecht (2001)Google Scholar
  9. 9.
    Odabasioglu, A., Celik, M., Pileggi, L.T.: PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17, 645–654 (1998)CrossRefGoogle Scholar
  10. 10.
    Odabasioglu, A., Celik, M., Pileggi, L.T.: Practical Considerations For Passive Reduction of RLC Circuits. In: Presented at International Conference on Computer Aided Design, San Jose, CA, USA (1999)Google Scholar
  11. 11.
    Kerns, K.J., Yang, A.T.: Stable and Efficient Reduction of Large, Multiport RC Networks by Pole Analysis via Congruence Transformations. In: Presented at Design Automation Conference, Las Vegas, NV, USA (1996)Google Scholar
  12. 12.
    Tsuk, M.J., Kong, A.J.: A Hybrid Method for the Calculation of the Resistance and Inductance of Transmission Lines with Arbitrary Cross Sections. IEEE Transactions on Microwave Theory and Techniques 39, 1338–1347 (1991)CrossRefGoogle Scholar
  13. 13.
    Kamon, M., Silveira, L.M., Smithhisler, C., White, J.: FastHenry User’s Guide, Research Laboratory of Electronics, Department of Electrical Engineering and Computer Science, Massachusetts Institute of TechnologyGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Jérôme Lescot
    • 1
  • François J. R. Clément
    • 1
  1. 1.Cadence Design Systems S.A., ZAC ChampfeuilletVoironFrance

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