Abstract
In this paper, a Floating-Point multiplier, supporting IEEE 754 Standard and full pipelined, is presented. A new architecture of dual-Way Multiplier is proposed. It can reduce 13.6% delay of critical path of adder tree according to full size multiplier without increasing area. The overall multiplier has a latency of 3 cycles and a throughput of 1 cycle for a single-precision or double-precision floating-point instruction. This multiplier has been verified on a FPGA and implemented in 0.18 Micron Standard Cell technology, with its frequency 384MHz and area 732902.25um2. This architecture is compared with other architectures under the same technique, and the result shows it is effective and efficient.
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© 2003 Springer-Verlag Berlin Heidelberg
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Zhou, X., Tang, Z. (2003). A New Architecture of a Fast Floating-Point Multiplier. In: Zhou, X., Xu, M., Jähnichen, S., Cao, J. (eds) Advanced Parallel Processing Technologies. APPT 2003. Lecture Notes in Computer Science, vol 2834. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39425-9_3
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DOI: https://doi.org/10.1007/978-3-540-39425-9_3
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20054-3
Online ISBN: 978-3-540-39425-9
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