Symmetry reduction is a technique to combat the state explosion problem in temporal logic model checking. Its use with symbolic representation has suffered from the prohibitively large BDD for the orbit relation. One suggested solution is to pre-compute a mapping from states to possibly multiple representatives of symmetry equivalence classes. In this paper, we propose a more efficient method that determines representatives dynamically during fixpoint iterations. Our scheme preserves the uniqueness of representatives. Another alternative to using the orbit relation is counter abstraction. It proved efficient for the special case of full symmetry, provided a conducive program structure. In contrast, our solution applies also to systems with less than full symmetry, and to systems where a translation into counters is not feasible. We support these claims with experimental results.


Symbolic Representation Symmetry Reduction Kripke Structure Reachability Analysis Orbit Relation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. [BG02]
    Barner, S., Grumberg, O.: Combining symmetry reduction and under-approximation for symbolic model checking. In: Brinksma, E., Larsen, K.G. (eds.) CAV 2002. LNCS, vol. 2404, p. 93. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  2. [Bry86]
    Bryant., R.E.: Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers (1986)Google Scholar
  3. [CC77]
    Cousot, P., Cousot, R.: Abstract interpretation: a unified lattice model for static analysis of programs by construction or approximation of fixpoints. In: Principles of Programming Languages, POPL (1977)Google Scholar
  4. [CE81]
    Clarke, E.M., Emerson, E.A.: The design and synthesis of synchronization skeletons using temporal logic. In: Logic of Programs, LOP (1981)Google Scholar
  5. [CEFJ96]
    Clarke, E.M., Enders, R., Filkorn, T., Jha, S.: Exploiting symmetry in temporal logic model checking. In: Formal Methods in System Design, FMSD (1996)Google Scholar
  6. [ES96]
    Emerson, E.A., Sistla, A.P.: Symmetry and model checking. In: Formal Methods in System Design, FMSD (1996)Google Scholar
  7. [ET99]
    Emerson, E.A., Trefler, R.J.: From asymmetry to full symmetry: New techniques for symmetry reduction in model checking. In: Pierre, L., Kropf, T. (eds.) CHARME 1999. LNCS, vol. 1703, pp. 142–157. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  8. [EW03]
    Emerson, E.A., Wahl, T.: On combining symmetry reduction and symbolic representation for efficient model checking. In: Geist, D., Tronci, E. (eds.) CHARME 2003. LNCS, vol. 2860, pp. 216–230. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  9. [God99]
    Godefroid, P.: Exploiting symmetry when model-checking software. In: Formal Methods for Protocol Engineering and Distributed Systems, FORTE (1999)Google Scholar
  10. [HBL+03]
    Hendriks, M., Behrmann, G., Larsen, K.G., Niebert, P., Vaandrager, F.W.: Adding symmetry reduction to uppaal. In: Larsen, K.G., Niebert, P. (eds.) FORMATS 2003. LNCS, vol. 2791. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  11. [ID96]
    Ip, C.N., Dill, D.L.: Better verification through symmetry. In: Formal Methods in System Design, FMSD (1996)Google Scholar
  12. [LS03]
    S. Lahiri, S. Seshia. UCLID: A Verification Tool for Infinite-State Systems (2003),
  13. [MD96]
    Melton, R., Dill, D.L.: Murϕ Annotated Reference Manual, rel. 3.1 (1996),
  14. [MS91]
    Mellor-Crummey, J.M., Scott, M.L.: Algorithms for scalable synchronization on shared-memory multiprocessors. In: ACM Transactions on Computer Systems, TOCS (1991)Google Scholar
  15. [PB99]
    Pandey, M., Bryant, R.E.: Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation. IEEE Transactions on Computer-Aided Design (1999)Google Scholar
  16. [PXZ02]
    Pnueli, A., Xu, J., Zuck, L.: Liveness with (0,1, ∞ )-Counter abstraction. In: Brinksma, E., Larsen, K.G. (eds.) CAV 2002. LNCS, vol. 2404, p. 107. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  17. [QS82]
    Quielle, J.-P., Sifakis, J.: Specification and verification of concurrent systems in cesar. In: 5th International Symposium on Programming (1982)Google Scholar
  18. [SGE00]
    Sistla, A.P., Gyuris, V., Emerson, E.A.: Smc: a symmetry-based model checker for verification of safety and liveness properties. ACM Transactions on Software Engineering and Methodology (2000)Google Scholar
  19. [Som01]
    Somenzi, F.: The CU Decision Diagram Package, release 2.3.1 (2001),

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • E. Allen Emerson
    • 1
  • Thomas Wahl
    • 1
  1. 1.Department of Computer Sciences and Computer Engineering Research CenterThe University of TexasAustinUSA

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