DESCOMP: A New Design Space Exploration Approach

  • Mario Schölzel
  • Peter Bachmann
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3432)


In this paper, we introduce a new approach in Design-Space-Exploration (DSE) for non-clustered VLIW architectures. It differs from existing techniques by using a “bottom-up” strategy. While other approaches start with the design of an architecture, followed by building a possible schedule, we firstly build a schedule and after that an architecture is synthesized, which is suitable to execute this schedule. So, the results can be obtained fully automatically and in very short time. Furthermore, we can explore arbitrary types of functional units without increasing the design space exploration time significantly. We evaluated our method and compared the obtained results to an existing DSE approach for clustered and non-clustered architectures. We almost always obtain better results in the case of non-clustered architectures. In many cases the ports of the register file are decreased, which, in consequence, leads to higher clock rates. Compared to the results for clustered architectures for some examples our non-clustered architecture is better than the best clustered one.


Basic Block Operation Type Interval Graph Register File Design Space Exploration 
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  1. 1.
    Lee, C., Potkonjak, M., Mangione-Smith, W.H.: MediaBench: A tool for evaluating and synthesizing multimedia and communications systems. In: Proc. of the 30th Annual International Symposium on Microarchitecture, pp. 330–335 (1997)Google Scholar
  2. 2.
    Hekstra, G.J., La Hei, G.D., Bingley, P., Sijstermans, F.W.: TriMedia CPU64 design space exploration. In: Proc. of the IEEE International Conference on Computer Design, pp. 599–606. IEEE Computer Society, Los Alamitos (1999)Google Scholar
  3. 3.
    DeMicheli, G.: Sythesis and Optimization of Digital Circuits (2004)Google Scholar
  4. 4.
    Snider, G.: Spacewalker: Automated Design Space Exploration for Embedded Computer Systems. Technical Report, HP Laboratories Palo Alto. HPL-2001-220 (2001)Google Scholar
  5. 5.
    Chaitin, G.J.: Register allocation and spilling via graph coloring. SIGPLAN Notices 17(6), 98–105 (1982)CrossRefMathSciNetGoogle Scholar
  6. 6.
    Guo, J., Hosemann, M., Fettweis, G.P.: Employing Compilers for Determining Architectural Features of Application-Specific DSPs. In: Proc. of International Conference on Parallel Computing in Electrical Engineering, pp. 39–44 (2004)Google Scholar
  7. 7.
    Dixit, K.: Performance SPECulations-benchmark, friend or foe. 7. International Symposium on High Performance Computer Architecture (Monterrey, Mexico) (2001)Google Scholar
  8. 8.
    Chu, M.L., Fan, K.C., Ravindran, R.A., Mahlke, S.A.: Cost-Sensitive Operation Partitioning for Synthesizing Custom Multicluster Datapath Architectures. In: Proc. 2nd Workshop on Application Specific Processors, pp. 40–47 (2003)Google Scholar
  9. 9.
    Paulin, P.G., Knight, J.P.: Force-directed scheduling in automatic data path synthesis. In: Procs. of the 24th ACM/IEEE Design Automation Conference, pp. 195–202 (1987)Google Scholar
  10. 10.
    Paolo, F., Geoffrey, B., Joseph, A.F., Giuseppe, D., Fred, H.: Lx: a technology platform for customizable VLIW embedded processing. In: The 27th Annual International Symposium on Computer architecture 2000, pp. 203–213. ACM Press, New York (2000)Google Scholar
  11. 11.
    Camposano, R.: From Behavior to Structure: High-Level Synthesis. IEEE Design & Test of Computers 7(5), 8–19 (1990)CrossRefGoogle Scholar
  12. 12.
    Rixner, S., Dally, W.J., Khailany, B., Mattson, P., Kapasi, U.J., Owens, J.D.: Register Organization for Media Processing. In: Procs. of the 6th. High- Performance Computer Architecture, pp. 375–386 (2000)Google Scholar
  13. 13.
    Aditya, S., Ramakrishna Rau, B., Jhonson, R.: Automatic Design of VLIW and EPIC Instruction Formats. Technical Report, HP Laboratories. HPL-1999-94 (2000)Google Scholar
  14. 14.
    Devadas, S., Newton, R.: Algorithms for Hardware Allocation in Data Path Synthesis. IEEE Transactions on Computer-Aided Design 8, 768–781 (1989)CrossRefGoogle Scholar
  15. 15.
    Lapinskii, V.S.: Algorithms for Compiler-Assisted Design-Space-Exploration of Clustered VLIW ASIP Datapaths. Dissertation, University of Texas at Austin (2001)Google Scholar
  16. 16.
    Lapinskii, V.S., Jacome, M.F., de. Veciana, G.A.: Application-Specific Clustered VLIW Datapaths: Early Exploration on a Parameterized Design Space. IEEE TCAD 21(8), 889–903 (2002)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Mario Schölzel
    • 1
  • Peter Bachmann
    • 1
  1. 1.Computer Science InstituteBrandenburg University of TechnologyCottbusGermany

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