Reusable Design of Inter-chip Communication Interfaces for Next Generation of Adaptive Computing Systems

  • Vincent Kotzsch
  • Jörg Schneider
  • Günther Döring
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3432)


The SoC (System-on-Chip) technology is used in small and flexible consumer electronic devices. SoCs include one or more microcontroller, memory, programmable logic, and the input/output logic control. Additionally, sophisticated SoCs support partial dynamic reconfiguration. Those are preconditions to build the next generation of adaptive computing systems which make it possible to implement selforganizing systems that are self-configuring and self-optimizing. The design of applications and the development of tools for system design are a great challenge. In this paper we describe an approach that is used to support the design of applications by generator tools. This approach allows the re-use and the generation of communication interfaces between the components in partial run-time reconfiguration (pRTR) systems. The generator tool approach based on a methodology which enables a formal representation of adaptive systems and its timing schedule control. We prove our methodology and generator approach by applications from the field of signal processing.


Field Programmable Gate Array Generator Tool Design Flow Communication Interface Operating Layer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Vincent Kotzsch
    • 1
  • Jörg Schneider
    • 2
  • Günther Döring
    • 1
  1. 1.Fraunhofer IIS, Branch Lab Design AutomationDresden
  2. 2.Department for VLSI-Design, Diagnostics and ArchitectureDresden University of TechnologyDresden

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