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Reusable Design of Inter-chip Communication Interfaces for Next Generation of Adaptive Computing Systems

  • Vincent Kotzsch
  • Jörg Schneider
  • Günther Döring
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3432)

Abstract

The SoC (System-on-Chip) technology is used in small and flexible consumer electronic devices. SoCs include one or more microcontroller, memory, programmable logic, and the input/output logic control. Additionally, sophisticated SoCs support partial dynamic reconfiguration. Those are preconditions to build the next generation of adaptive computing systems which make it possible to implement selforganizing systems that are self-configuring and self-optimizing. The design of applications and the development of tools for system design are a great challenge. In this paper we describe an approach that is used to support the design of applications by generator tools. This approach allows the re-use and the generation of communication interfaces between the components in partial run-time reconfiguration (pRTR) systems. The generator tool approach based on a methodology which enables a formal representation of adaptive systems and its timing schedule control. We prove our methodology and generator approach by applications from the field of signal processing.

Keywords

Field Programmable Gate Array Generator Tool Design Flow Communication Interface Operating Layer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Boden, M., Schneider, J., Feske, K., Rülke, S.: Enhanced Reusability for SoC-based HW/SW Co-Design. In: Euromicro Symposium on Digital System Design, Dortmund, Germany (September 4-6, 2002)Google Scholar
  2. 2.
    Erni, A., Reichmuth, S.: Inter-Task-Communication in Reconfigurable Operating Systems Masters Thesis, ETH Zürich (2003)Google Scholar
  3. 3.
    Haase, J. Schneider u.a.: Design of a Reed Solomon decoder using partial dynamic reconfi- guration of Xilinx Virtex FPGAs-a case study, In: DATE 2002, Paris, France ( March 4-8, 2002) Google Scholar
  4. 4.
    Horta, E., Lockwood, J.W.: PARBIT: a tool to transform bitfiles to implement partial recon- figuration of field programmable gate arrays (FPGAs), Tech. Rep. WUCS-01-13, Washington University in Saint Louis, Department of Computer Science (July 6, 2001)Google Scholar
  5. 5.
    Kasprzyk, N., Koch, A.: Verbesserte Hardware-Software-Partitionierung für Adaptive Computer. In: 17th International Conference on Architecture of Computing Systems, ARCS 2004, Augsburg, Germany, March 23-26 (2004)Google Scholar
  6. 6.
    Koegst, M., Rülke, S.: Conditions for the Number of Errors in a Reed-Solomon Codec. In: 3th int. symposium on mobile multimedia systems and applications, MMSA 2002, Delft, Netherlands (December 2002)Google Scholar
  7. 7.
    Kotzsch, V.: Entwurfsautomatisierung von internen Kommunikationsschnittstellen in dynamisch rekonfigurierbaren Systems on Chips (SoCs), Diploma Thesis, Hochschule für Technik und Wirtschaft Dresden (FH) (September 2004)Google Scholar
  8. 8.
    Lim, D., Peattie, M.: Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulation, Application Note XAPP 290, Xilinx Inc., (November 2003)Google Scholar
  9. 9.
    Peterson, W.W.: Error-correcting codes. MIT Press, Cambridge (1994)Google Scholar
  10. 10.
    Schneider, J., Kotzsch, V.: Wiederverwendungsgerechte Codegenerierung von FECApplikationen für dynamisch rekonfigurierbare Systeme. In: 17th International Conference on Architecture of Computing Systems, ARCS 2004, Workshop - Dynamisch Rekonfigurierbare Systeme, Augsburg, Germany (March 26, 2004)Google Scholar
  11. 11.
    Schneider, J., Kotzsch, V., Rülke, S.: Demonstrator: Reuse Automation for Reconfigurable System-on-Chip Design within a DVB Environment. In: International Conference on Parallel Computing in Electrical Engineering, PARELEC 2004, Dresden, Germany (September 7-10, 2004)Google Scholar
  12. 12.
    Schneider, J., Boden, M., Rülke, S.: Eine wiederverwendungsgerechte Entwurfsmethodik für rekonfigurierbare SoC-Architekturen. In: GI/ITG/GMM Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Tübingen, Germany (February 25-27, 2002)Google Scholar
  13. 13.
    Tangen, U.: Selbstorganisation und Evolution elektronischer Hardware, GMD Spiegel (May 2000)Google Scholar
  14. 14.
    Thorvinger, J.: Dynamic Partial Reconfiguration of an FPGA for Computational Hardware Support, Diploma Thesis, Lund Institute of Technology (June 2004)Google Scholar
  15. 15.
    Virtex FPGA Series Configuration and Readback, Application Note XAPP 137, Xilinx Inc., (July 11, 2002) Google Scholar
  16. 16.
    Virtex 2.5V Field Programmable Gate Arrays, Product Specification, DS003-1, Xilinx Inc., (April 2, 2001) Google Scholar
  17. 17.
    Walder, H., Steinegger, S., Platzner, M.: Implementation of a Runtime Environment for Reconfigurable Hardware Operating Systems. In: Swiss Federal Institute of Technology Zurich (ETH) Computer Engineering and Networks Laboratory, TIK Report Nr. 195, Zurich, Switzerland (June 2004)Google Scholar
  18. 18.
  19. 19.
  20. 20.
  21. 21.

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Vincent Kotzsch
    • 1
  • Jörg Schneider
    • 2
  • Günther Döring
    • 1
  1. 1.Fraunhofer IIS, Branch Lab Design AutomationDresden
  2. 2.Department for VLSI-Design, Diagnostics and ArchitectureDresden University of TechnologyDresden

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