Timed I/O Test Sequences for Discrete Event Model Verification

  • Ki Jung Hong
  • Tag Gon Kim
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3397)


Model verification examines the correctness of a model implementation with respect to a model specification. While being described from model specification, implementation prepares to execute or evaluate a simulation model by a computer program. Viewing model verification as a program test this paper proposes a method for generation of test sequences that completely covers all possible behavior in specification at an I/O level. Timed State Reachability Graph (TSRG) is proposed as a means of model specification. Graph theoretical analysis of TSRG has generated a test set of timed I/O event sequences, which guarantees 100% test coverage of an implementation under test.


Test Sequence Discrete Event System Conformance Test Basic Loop Loop Path 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Banks, J., Gerstein, D., Searles, S.P.: Modeling process, validation, and verification of complex simulations: A survey. S.C.S Methodology and Validation, simulation series 19(1), 13–18 (1988)Google Scholar
  2. 2.
    Concepcion, Zeigler, B.P.: DEVS formalism: a framework for hierarchical model development. IEEE Trans. Software Eng. 14(2), 228–241 (1988)CrossRefGoogle Scholar
  3. 3.
    Chan, W.Y.L., Vuong, C.T., Otp, M.R.: An improved protocol test generation procedure based on UIOS. ACM SIGCOMM Comp. Commun. Review, Symposium proc. communi. arch. & protocols 19, 283–294 (1989)CrossRefGoogle Scholar
  4. 4.
    Dahbura, A.T., Sabnani, K.K., Ümit Uyar, M.: Formal nethods for generating protocol conformance test sequences. Proc. of the IEEE 78, 1317–1325 (1990)CrossRefGoogle Scholar
  5. 5.
    Lee, D., Yannakakis, M.: Principles and methods of testing finite state machines- A survey. Proc of the IEEE 84, 1090–1123 (1996)CrossRefGoogle Scholar
  6. 6.
    En-Nouaary, A., Dssouli, R., Khendek, F.: Timed Wp-method: Testing real-time systems. IEEE Trans. Software Eng. 28, 1023–1038 (2002)CrossRefGoogle Scholar
  7. 7.
    Hong, K.J., Kim, T.G.: A Verification Of Time Constrained Simulation Model Using Test Selection:A New Approach. (2004) (In preparation)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Ki Jung Hong
    • 1
  • Tag Gon Kim
    • 1
  1. 1.Dept. of EECSKorea Advanced Institute of Science and Technology (KAIST)DaejeonRepublic of Korea

Personalised recommendations