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Timed I/O Test Sequences for Discrete Event Model Verification

  • Ki Jung Hong
  • Tag Gon Kim
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3397)

Abstract

Model verification examines the correctness of a model implementation with respect to a model specification. While being described from model specification, implementation prepares to execute or evaluate a simulation model by a computer program. Viewing model verification as a program test this paper proposes a method for generation of test sequences that completely covers all possible behavior in specification at an I/O level. Timed State Reachability Graph (TSRG) is proposed as a means of model specification. Graph theoretical analysis of TSRG has generated a test set of timed I/O event sequences, which guarantees 100% test coverage of an implementation under test.

Keywords

Test Sequence Discrete Event System Conformance Test Basic Loop Loop Path 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Ki Jung Hong
    • 1
  • Tag Gon Kim
    • 1
  1. 1.Dept. of EECSKorea Advanced Institute of Science and Technology (KAIST)DaejeonRepublic of Korea

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