Abstract
This work proposes a compact implementation of the AES S-box using composite field arithmetic in GF(((22)2)2). It describes a systematic exploration of different choices for the irreducible polynomials that generate the extension fields. It also examines all possible transformation matrices that map one field representation to another. We show that the area of Satoh’s S-box, which is the most compact to our knowledge, is at least 5% away from an optimal solution. We implemented this optimal solution and Satoh’s design using a 0.18 μm standard cell library.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
FIPS Pub. 197: Specification for the AES (November 2001), http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
Alam, M., Badawy, W., Jullien, G.: A novel pipelined threads architecture for aes encryption algorithm. In: Schulte, M., Bhattacharyya, S., Burgess, N., Schreiber, R. (eds.) Proceedings of the IEEE International Conference on Application-Specific System, Architectures, and Processors (ASAP), San Jose, CA, USA, July 17-19, pp. 296–302. IEEE Computer Society Press, Los Alamitos (2002)
Chodowiec, P., Gaj, K.: Very compact FPGA implementation of the AES algorithm. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 319–333. Springer, Heidelberg (2003)
Daemen, J., Rijmen, V.: AES proposal: Rijndael (September 2001), http://csrc.nist.gov/CryptoToolkit/aes/rijndael/Rijndael.pdf
Daemen, J., Rijmen, V.: The design of Rijndael: AES–The Advanced Encryption Standard. Springer, Heidelberg (2002)
Daemen, J., Rijmen, V.: Security of a wide trail design. In: Menezes, A., Sarkar, P. (eds.) INDOCRYPT 2002. LNCS, vol. 2551, pp. 1–11. Springer, Heidelberg (2002)
Fischer, V., Drutarovský, M.: Two methods of Rijndael implementation in reconfigurable hardware. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 77–92. Springer, Heidelberg (2001)
Gaj, K., Chodowiec, P.: Fast implementation and fair comparison of the final candidates for advanced encryption standard using field programmable gate arrays. In: Naccache, D. (ed.) CT-RSA 2001. LNCS, vol. 2020, p. 84. Springer, Heidelberg (2001)
Guajardo, J., Paar, C.: Efficient algorithms for elliptic curve cryptosystems. In: Kaliski Jr., B.S. (ed.) CRYPTO 1997. LNCS, vol. 1294, pp. 342–356. Springer, Heidelberg (1997)
Jdrvinen, K., Tommiska, M., Skyttd, J.: A fully pipelined memoryless 17.8 Gbps AES-128 encyptor. In: Proceedings of the 11th ACM International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, CA, USA (February 23-25, 2003)
Kuo, H., Verbauwhede, I.: Architectural optimization for a 1.82Gbits/sec VLSI implementation of the AES rijndael algorithm. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 51–64. Springer, Heidelberg (2001)
Lu, C.-C., Tseng, S.-Y.: Integrated design of AES (Advanced Encryption Standard) encrypter and decrypter. In: Schulte, M., Bhattacharyya, S., Burgess, N., Schreiber, R. (eds.) Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP), San Jose, CA, USA, July 17-19, pp. 277–285. IEEE Computer Society Press, Los Alamitos (2002)
Macchetti, M., Bertoni, G.: Hardware implementation of the Rijndael Sbox: A case study. ST Journal of system research, 84–91 (2002)
McLoone, M., McCanny, J.V.: High performance single-chip FPGA Rijndael algorithm implementations. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 65–76. Springer, Heidelberg (2001)
Paar, C.: Efficient VLSI Architectures for Bit-Parallel Computation in Galois Fields. PhD thesis, Institute for Experimental Mathematics, University of Essen, Germany (1994)
Rudra, A., Dubey, P.K., Jutla, C.S., Kumar, V., Rao, J.R., Rohatgi, P.: Efficient Rijndael encryption implementation with composite field arithmetic. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 171–184. Springer, Heidelberg (2001)
Satoh, A., Morioka, S., Takano, K., Munetoh, S.: A compact Rijndael hardware architecture with S-Box optimization. In: Boyd, C. (ed.) ASIACRYPT 2001. LNCS, vol. 2248, pp. 239–254. Springer, Heidelberg (2001)
Standaert, F.-X., Rouvroy, G., Quisquater, J.-J., Legat, J.-D.: Efficient implemen ation of rijndael encryption in reconfigurable hardware: Improvements and design tradeoffs. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 334–350. Springer, Heidelberg (2003)
Verbauwhede, I., Schaumont, P., Kuo, H.: Design and performance testing of a2.29-Gb/s Rijndael processor. IEEE Journal of Solid-State Circuits 38(3), 569–572 (2003)
Wolkerstorfer, J.: Dual-field arithmetic unit for GF(p) and GF(2m). In: Kaliski Jr., B.S., Koç, Ç.K., Paar, C. (eds.) CHES 2002. LNCS, vol. 2523, pp. 500–514. Springer, Heidelberg (2003)
Wolkerstorfer, J., Oswald, E., Lamberger, M.: An ASIC implementation of the AES S-Boxes. In: Preneel, B. (ed.) CT-RSA 2002. LNCS, vol. 2271, pp. 67–78. Springer, Heidelberg (2002)
Wu, S.-Y., Lu, S.-C., Laih, C.S.: Design of AES based on dual cipher and composite field. In: Okamoto, T. (ed.) CT-RSA 2004. LNCS, vol. 2964, pp. 25–38. Springer, Heidelberg (2004)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Mentens, N., Batina, L., Preneel, B., Verbauwhede, I. (2005). A Systematic Evaluation of Compact Hardware Implementations for the Rijndael S-Box. In: Menezes, A. (eds) Topics in Cryptology – CT-RSA 2005. CT-RSA 2005. Lecture Notes in Computer Science, vol 3376. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30574-3_22
Download citation
DOI: https://doi.org/10.1007/978-3-540-30574-3_22
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-24399-1
Online ISBN: 978-3-540-30574-3
eBook Packages: Computer ScienceComputer Science (R0)