Abstract
We designed a cycle-accurate user-retargetable instruction-set simulator (UR-ISS) based on architecture description language (ADL) which is suitable for system-on-chip (SoC) design. It uses a new scheduling method based on process control. It is effective for schedulingmulti-cycle instructions and asynchronous events to a pipeline such as interrupts and exceptions frequently found in SoCs. The proposed UR-ISS consists of a byte-code compiler (BCC) and a virtual machine (VM); The BCC translates ADL semantics into byte-codes and the VM executes them. We have investigated that the UR-ISS is 5.5 times faster than HDL models and 2.5 times faster than System-C models on average. We also applied the UR-ISS for CALMRISC32TMduring its development and obtained good results for functional validation.
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© 2004 Springer-Verlag Berlin Heidelberg
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Yang, H., Lee, M. (2004). Design of a Cycle-Accurate User-Retargetable Instruction-Set Simulator Using Process-Based Scheduling Scheme. In: Zhang, J., He, JH., Fu, Y. (eds) Computational and Information Science. CIS 2004. Lecture Notes in Computer Science, vol 3314. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30497-5_42
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DOI: https://doi.org/10.1007/978-3-540-30497-5_42
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-24127-0
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