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International Conference on Formal Techniques for Networked and Distributed Systems

FORTE 2004: Applying Formal Methods: Testing, Performance, and M/E-Commerce pp 209–219Cite as

Modeling and Analysis of Dual Block Multithreading

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 3236))

Abstract

Instruction level multithreading is a technique for tolerating long–latency operations (e.g., cache misses) by switching the processor to another thread instead of waiting for the completion of a lengthy operation. In block multithreading, context switching occurs for each initiated long–latency operation. However, processor cycles during pipeline stalls as well as during context switching are not used in typical block multithreading, reducing the performance of a processor. Dual block multithreading introduces a second active thread which is used for instruction issuing whenever the original (main) thread becomes inactive. Dual block multithreading can be regarded as a simple and specialized case of simultaneous multithreading when two (simultaneous) threads are used to issue instructions for a single pipeline. The paper develops a simple timed Petri net model of a dual block multithreading and uses this model to estimate the performance improvements of the proposed dual block multithreading.

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Author information

Authors and Affiliations

  1. Department of Computer Science, Memorial University, St.John’s, Canada, A1B 3X5

    W. M. Zuberek

Authors
  1. W. M. Zuberek
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Editor information

Editors and Affiliations

  1. Dept. Sistemas Informáticos y Programación Facultad de Informática, Universidad Complutense de Madrid, 28040,, Madrid, Spain

    Manuel Núñez

  2. CIT, Zayed University, Dubai, United Arab Emirates, United Arab Emirates

    Zakaria Maamar

  3. Dept. de Sistemas Informáticos Escuela Politécnica Superior, Universidad Castilla-La Mancha, 02071, Albacete, Spain

    Fernando L. Pelayo

  4. Business Informatics and Systems Engineering, University of Augsburg, Universitätsstraße 16, 86135, Augsburg, Germany

    Key Pousttchi

  5. Dept. Sistemas Informáticos y Computación, Facultad de Informática, Universidad Complutense de Madrid, Madrid, Spain

    Fernando Rubio

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© 2004 Springer-Verlag Berlin Heidelberg

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Zuberek, W.M. (2004). Modeling and Analysis of Dual Block Multithreading. In: Núñez, M., Maamar, Z., Pelayo, F.L., Pousttchi, K., Rubio, F. (eds) Applying Formal Methods: Testing, Performance, and M/E-Commerce. FORTE 2004. Lecture Notes in Computer Science, vol 3236. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30233-9_16

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  • DOI: https://doi.org/10.1007/978-3-540-30233-9_16

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-23169-1

  • Online ISBN: 978-3-540-30233-9

  • eBook Packages: Springer Book Archive

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