Abstract
In this tutorial, we give an introduction to the increasingly important effect of leakage in recent and upcoming technologies. The sources of leakage such as subthreshold leakage, gate leakage, pn-junction leakage and further GIDL, hot-carrier effect and punchthrough are identified and analyzed separately and also under PTV variations.
Since leakage will dominate power consumption in future technologies, we also review leakage optimization techniques and leakage estimation approaches supporting optimizations especially at higher abstraction levels.
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Helms, D., Schmidt, E., Nebel, W. (2004). Leakage in CMOS Circuits – An Introduction. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_5
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DOI: https://doi.org/10.1007/978-3-540-30205-6_5
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