Abstract
While the feature size of integrated circuits decreases with every technology node, the impact of interconnect delay on the total delay increases. Thus, minimizing the wirelength becomes one of the most important tasks in physical design of high performance circuits.
In this paper we present a 3-D design flow for vertical integrated circuits. Our floorplanning and placement results show reductions of both total wirelength and lengths of the longest nets up to 50%. Thus, we demonstrate the capability of significant interconnect delay reduction using vertical integration.
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Kaya, I., Salewski, S., Olbrich, M., Barke, E. (2004). Wirelength Reduction Using 3-D Physical Design. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_47
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DOI: https://doi.org/10.1007/978-3-540-30205-6_47
Publisher Name: Springer, Berlin, Heidelberg
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