Abstract
In archiectural synthesis, scheduling and resource allocation are important steps. During the early stage of the design, imprecise information is unavoidable. Under the imprecise system characteristics and constraints, this paper proposes a polynomial-time scheduling algorithm which minimizes both functional units and registers while scheduling. The algorithm can be used in design exploration for exploring the tradeoff between latency and register counts and selecting a solution with satisfactory performance and cost. The experiments show that we can achieve a schedule with the same acceptable degree while saving register upto 37% compared to the traditional algorithm.
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Chantrapornchai, C., Surakumpolthorn, W., Sha, E. (2004). Efficient Scheduling for Design Exploration with Imprecise Latency and Register Constraints. In: Yang, L.T., Guo, M., Gao, G.R., Jha, N.K. (eds) Embedded and Ubiquitous Computing. EUC 2004. Lecture Notes in Computer Science, vol 3207. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30121-9_25
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DOI: https://doi.org/10.1007/978-3-540-30121-9_25
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22906-3
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