Abstract
Hyperreconfigurable architectures adapt their reconfiguration abilities during run time in order to achieve fast dynamic reconfiguration. Models for such architectures have been proposed that change their ability for reconfiguration during hyperreconfiguration steps and in ordinary reconfiguration steps reconfigure the actual contexts for a computation within the limits that have been set by the last hyperreconfiguration step. In this paper we study algorithmic aspects of how to optimally decide what hyperreconfiguration steps should be done during a computation in order to minimize the total time necessary for hyperreconfiguration and ordinary reconfiguration. It is shown that the general problem is NP-hard but fast polynomial time algorithms are given to solve this problem on different types of hyperreconfigurable architectures. These include newly introduced architectures that use a cache to store hypercontexts. We define an example hyperreconfigurable architecture and illustrate the introduced concepts for three application problems.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Bolotski, M., DeHon, A., Knight Jr., T.F.: Unifying FPGAs and SIMD Arrays. In: Proc. FPGA 1994 – 2nd International ACM/SIGDAWorkshop on FPGAs, pp. 1–10 (1994)
Bondalapati, K., Prasanna, V.K.: Reconfigurable Computing: Architectures, Models and Algorithms. In: Proc. Reconfigurable Architectures Workshop, IPPS (1997)
Compton, K., Hauck, S.: Configurable Computing: A Survey of Systems and Software. ACM Computing Surveys 34(2), 171–210 (2002)
Dandalis, A., Prasanna, V.K.: Configuration Compression for FPGA-based Embedded Systems. In: Proc. ACM Int. Symposium on Field-Programmable Gate Arrays, pp. 173–182 (2001)
Haubelt, C., Teich, J., Richter, K., Ernst, R.: System Design for Flexibility. In: Proc. 2002 Design, Automation and Test in Europe, pp. 854–861 (2002)
Hauck, S., Li, Z., Rolim, J.D.P.: Configuration Compression for the Xilinx XC6200 FPGA. IEEE Trans. on CAD of Integrated Circuits and Systems 8, 1107–1113 (1999)
Kannan, P., Balachandran, S., Bhatia, D.: On Metrics for Comparing Routability Estimation Methods for FPGAs. In: Proc. 39th Design Automation Conference, pp. 70–75 (2002)
Koester, M., Teich, J. (Self-)reconfigurable Finite State Machines: Theory and Implementation. In: Proc. 2002 Design, Automation and Test in Europe, pp. 559–566 (2002)
Lange, S., Middendorf, M.: Hyperreconfigurable Architectures for Fast Runtime Reconfiguration. In: Proceedings of 2004 IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), Napa Valley, USA (2004) (to appear)
Lange, S., Middendorf, M.: Models and Reconfiguration Problems for Multi Task Hyperreconfigurable Architectures. In: Proc. RAW 2004, Santa Fe (2004) (to appear)
Lee, K.K., Wong, D.F.: Incremental Reconfiguration of Multi-FPGA Systems. In: Proc. Tenth ACM International Symposium on Field Programmable Gate Arrays, pp. 206–213 (2002)
Ling, X.P., Amano, H.: WASMII: a Data Driven Computer on a Virtual Hardware. In: Proc. of the IEEE Workshop on FPGAs for Custom Computing Machines, pp. 33–42 (1993)
Lee, T.-M., Henkel, J., Wolf, W.: Dynamic Runtime Re-Scheduling Allowing Multiple Implementations of a Task for Platform-Based Designs. In: Proc. 2002 Design, Automation and Test in Europe, pp. 296–301 (2002)
Puttegowda, K., Lehn, D.I., Park, J.H., Athanas, P., Jones, M.: Context Switching in a Run-Time Reconfigurable System. The Journal of Supercomputing 26(3), 239–257 (2003)
Sidhu, R.P.S., Wadhwa, S., Mei, A., Prasanna, V.K.: A Self-Reconfigurable Gate Array Architecture. In: Grünbacher, H., Hartenstein, R.W. (eds.) FPL 2000. LNCS, vol. 1896, pp. 106–120. Springer, Heidelberg (2000)
Teich, M., Fekete, S., Schepers, J.: Compile-Time Optimization of Dynamic Hardware Reconfigurations. In: Proc. Int. Conf. on Parallel and Distributed Processing Techniques and Applications (PDPTA 1999), Las Vegas, U.S.A (1999)
Wadhwa, S., Dandalis, A.: Efficient Self-Reconfigurable Implementations Using On-chip Memory. In: Grünbacher, H., Hartenstein, R.W. (eds.) FPL 2000. LNCS, vol. 1896, pp. 443–448. Springer, Heidelberg (2000)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Lange, S., Middendorf, M. (2004). The Partition into Hypercontexts Problem for Hyperreconfigurable Architectures. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_27
Download citation
DOI: https://doi.org/10.1007/978-3-540-30117-2_27
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22989-6
Online ISBN: 978-3-540-30117-2
eBook Packages: Springer Book Archive