Abstract
In this paper we propose a new routing architecture, based on a new switch called T-switch, which we implement in two different versions. Our approach is based on a modified disjoint topology in order to reduce the number of buffers required and on the introduction of a decoding stage between configuration memories and the switch to reduce the number of SRAM cells. This solution is particularly suitable for multi-context arrays, where configuration memory cells need to be replicated as many times as the number of contexts.
The buffered switch proposed has been implemented in two different gate array architectures, in order to evaluate its effectiveness. The results show that the T-switch routing architecture reduces the device area occupation up to 29% in a 4-context array. We also show that the critical path delay is reduced, while routability is substantially unaffected.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
DeHon, A.: DPGA-Coupled Microprocessors: Commodity ICs for the Early 21st Century. In: Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, California, April 1994, pp. 31–39 (1994)
Trimberger, S., Carberry, D., Jhonson, A., Wong, J.: A Time Multiplexed FPGA. In: Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, California, April 1997, pp. 34–40 (1997)
Sheng, M., Rose, J.: Mixing buffers and pass transistors in FPGA routing architectures. In: ACM/SIGDA International Symposium on FPGAs, pp. 75–84 (February 2001)
Lemieux, G., Lewis, D.: Circuit Design of Routing Switches. In: ACM/SIGDA International Symposium on FPGAs (February 2002)
DeHon, A.: Entropy, Counting, and Programmable Interconnect. In: ACM/SIGDA International Symposium on FPGAs (February 1996)
Lodi, A., Ciccarelli, L., Cappelli, A., Campi, F.: M, Toma. Decoder-based interconnect structure for multi-context FPGAs. Electronic Letters 38, 362–364 (2003)
Betz, V., Rose, J.: VPR: A New Packing, Placement, and Routing Tool for FPGA Research. In: International Workshop on Field Programmable Logic and Applications (September 1997)
Lodi, A., Toma, M., Campi, F., Cappelli, A., Canegallo, R., Guerrieri, R.: A Pipelined Configurable Gate Array for Embedded Processors. In: Proceedings of the 11th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2003, pp. 21–30 (2003)
Mucci, C., Chiesa, C., Lodi, A., Toma, M., Campi, F.: A C-based Algorithm Development Flow for a Reconfigurable Processor Architecture. In: International Symposium on System-on-Chip, Tampere, Finland (2003)
Sentovich, E.M., Singh, K.J., Lavagno, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H., Stephan, P.R., Brayton, R.K., Sangiovanni-Vincentelli, A.: SIS: A System for Sequential Circuit Synthesis. UCB/ERL M92/41 (1992)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Lodi, A., Giansante, R., Chiesa, C., Ciccarelli, L., Campi, F., Toma, M. (2004). Compact Buffered Routing Architecture. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_20
Download citation
DOI: https://doi.org/10.1007/978-3-540-30117-2_20
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22989-6
Online ISBN: 978-3-540-30117-2
eBook Packages: Springer Book Archive