Abstract
Synthesis of digital signal processing (DSP) software from dataflow-based formal models is an effective approach for tackling the complexity of modern DSP applications. In this paper, an efficient method is proposed for applying subroutine call instantiation of module functionality when synthesizing embedded software from a dataflow specification. The technique is based on a novel recursive decomposition of subgraphs in a cluster hierarchy that is optimized for low buffer size. Applying this technique, one can achieve significantly lower buffer sizes than what is available for minimum code size inlined schedules, which have been the emphasis of prior software synthesis work. Furthermore, it is guaranteed that the number of procedure calls in the synthesized program is polynomially bounded in the size of the input dataflow graph, even though the number of module invocations may increase exponentially. This recursive decomposition approach provides an efficient means for integrating subroutine-based module instantiation into the design space of DSP software synthesis. The experimental results demonstrate a significant improvement in buffer cost, especially for more irregular multi-rate DSP applications, with moderate code and execution time overhead.
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Ko, MY., Murthy, P.K., Bhattacharyya, S.S. (2004). Compact Procedural Implementation in DSP Software Synthesis Through Recursive Graph Decomposition. In: Schepers, H. (eds) Software and Compilers for Embedded Systems. SCOPES 2004. Lecture Notes in Computer Science, vol 3199. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30113-4_5
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DOI: https://doi.org/10.1007/978-3-540-30113-4_5
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