Skip to main content

A Fault-Tolerant Single-Chip Multiprocessor

  • Conference paper
Advances in Computer Systems Architecture (ACSAC 2004)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 3189))

Included in the following conference series:

Abstract

The microprocessor is a crucial component of a reliable system. With improvement in semiconductor manufacturing, more and more transistors may be integrated into a single chip with increased potential detriment to dependability. Fault-tolerant single-chip multiprocessors offer an ideal architecture for achieving high availability while maintaining high performance. The design of a fault-tolerant single-chip multiprocessor is described – from hardware redundancy to software support and firmware information strategies. The design aims at masking the influences of errors and automatically correcting system states, which differs from traditional approaches which mainly target errors in the memory and I/O subsystems. Dynamic recovery and reconfiguration are also described to provide adequate protection from catastrophic failure of the system.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Constantinescu, C.: Trends and Challenges in VLSI Circuit Reliability. IEEE Micro 23(4), 14–19 (2003)

    Article  Google Scholar 

  2. Lee, S.-W., Song, Y.-S., et al.: Raptor: A Single Chip Multiprocessor. In: The First IEEE Asia Pacific Conference on ASIC, pp. 217–220 (1999)

    Google Scholar 

  3. Codrescu, L., Scott Wills, D., Meindl, J.: Architecture of Atlas Chip- Multiprocessor: Dynamically Parallelizing Irregular Applications. IEEE Transactions on Computers 50(1), 67–82 (2001)

    Article  Google Scholar 

  4. Nickolls, J., Madar III, L.J.: Calisto: A Low-Power Single-Chip Multiporcessor Communications Platform. IEEE Micro 23(4), 29–43 (2003)

    Article  Google Scholar 

  5. Bossen, D.C., Kitamorn, A., Reick, K.F., Floyd, M.S.: Fault-tolerant Design of the IBM pSeries 690 System using POWER4 Processor Technology. IBM J. RES. & DEV 46(1), 77–86 (2002)

    Article  Google Scholar 

  6. Bossen, D.C., Tendler, J.M., Reick, K.: POWER4 System Design for High Reliability. IEEE Micro 22(2), 16–24 (2002)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2004 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Yao, W., Wang, D., Zheng, W. (2004). A Fault-Tolerant Single-Chip Multiprocessor. In: Yew, PC., Xue, J. (eds) Advances in Computer Systems Architecture. ACSAC 2004. Lecture Notes in Computer Science, vol 3189. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30102-8_12

Download citation

  • DOI: https://doi.org/10.1007/978-3-540-30102-8_12

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-23003-8

  • Online ISBN: 978-3-540-30102-8

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics