Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches

  • Rajeev Balasubramonian
  • Viji Srinivasan
  • Sandhya Dwarkadas
  • Alper Buyuktosunoglu
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3164)


As technology scales and processor speeds improve, power has become a first-order design constraint in all aspects of processor design. In this paper, we explore the use of criticality metrics to reduce dynamic and leakage energy within data caches. We leverage the ability to predict whether an access is in the application’s critical path to partition the accesses into multiple streams. Accesses in the critical path are serviced by a high-performance (hot) cache bank. Accesses not in the critical path are serviced by a lower energy (and lower performance (cold)) cache bank. The resulting organization is a physically banked cache with different levels of energy consumption and performance in each bank. Our results demonstrate that such a classification of instructions and data across two streams can be achieved with high accuracy. Each additional cycle in the cold cache access time slows performance down by only 0.8%. However, such a partition can increase contention for cache banks and entail non-negligible hardware overhead. While prior research has effectively employed criticality metrics to reduce power in arithmetic units, our analysis shows that the success of these techniques are limited when applied to data caches.


Critical Path Data Block Data Cache Cache Line Cache Block 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Rajeev Balasubramonian
    • 1
  • Viji Srinivasan
    • 2
  • Sandhya Dwarkadas
    • 3
  • Alper Buyuktosunoglu
    • 2
  1. 1.School of ComputingUniversity of UtahUSA
  2. 2.IBM T.J. Watson Research CenterUSA
  3. 3.Department of Computer ScienceUniversity of RochesterUSA

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