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The Synergy Between Power-Aware Memory Systems and Processor Voltage Scaling

  • Xiaobo Fan
  • Carla S. Ellis
  • Alvin R. Lebeck
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3164)

Abstract

Energy consumption is becoming a limiting factor in the development of computer systems for a range of application domains. Since processor performance comes with a high power cost, there is increased interest in scaling the CPU voltage and clock frequency. Dynamic Voltage Scaling (DVS) is the technique for exploiting hardware capabilities to select an appropriate clock rate and voltage to meet application requirements at the lowest energy cost. Unfortunately, the power and performance contributions of other system components, in particular memory, complicate some of the simple assumptions upon which most DVS algorithms are based.

We show that there is a positive synergistic effect between DVS and power-aware memories that can transition into lower power states. This combination can offer greater energy savings than either technique alone (89% vs. 39% and 54%). We argue that memory-based criteria—information that is available in commonly provided hardware counters—are important factors for effective speed-setting in DVS algorithms and we develop a technique to estimate overall energy consumption based on them.

Keywords

Power-Aware Memory System DVS Control Policy Synergy 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Xiaobo Fan
    • 1
  • Carla S. Ellis
    • 1
  • Alvin R. Lebeck
    • 1
  1. 1.Department of Computer ScienceDuke UniversityDurhamUSA

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