A QoS Provisioned CIOQ ATM Switch with m Internal Links

  • C. R. dos Santos
  • S. Motoyama
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3124)


A QoS provisioned CIOQ ATM switch with m internal links is proposed in this paper. In the proposed switch the incoming cells at each input port are discriminated into service classes. For each service class, at each input port, a single buffer is provided whereas each output port needs m buffers, where m is the number of internal links (or channels) that connect each input port to each output port. The proposed switch uses physical internal links instead of time division, thus no speedup is required. The results of simulation of proposed switch using simple priority schedulers show that for m≥3 the number of cell waiting at input queue is small, less than 0,1 cells in average, independent of service classes. The proposed switch has also the feature that facilitates the choice of scheduler in order to satisfy the QoS of each class of service.


Schedule Algorithm Output Port Input Port Service Class Output Buffer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Motoyama, S., Petr, D.W., Frost, V.S.: Input – queued switch based on a scheduling algorithm. Electronics Letters 31(14), 1127–1128 (1995)CrossRefGoogle Scholar
  2. 2.
    McKeown, N., Varaiya, P., Walrand, J.: Scheduling cells in an Input-Queued Switch. Electronics Letter 3(11), 323–325 (1993)Google Scholar
  3. 3.
    Motoyama, S., Ono, L.M., Mavigno, M.C.: An iterative cell scheduling algorithm for ATM input-queued switch with service class priority. IEEE communications Letters 3(11), 323–325 (1999)CrossRefGoogle Scholar
  4. 4.
    Anderson, T.E., Owicki, S.S., Saxe, J.B., Tacker, C.P.: High Speed Switch Scheduling for Local Area Networks. In: Proc. Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, October 1992, pp. 98–110 (1992)Google Scholar
  5. 5.
    Genda, K., Yamanaka, N., Doi, Y.: A High-Speed ATM Switch that uses a Simple Retray Algorithm and Small Input Buffers. IEICE Trans. Commun. E76-B(7) (July 1993)Google Scholar
  6. 6.
    Minkenberg, C., Engbersen, T.: A combined Input and Output Queued Packet-Switched System Based on PRIZMA Switch-on-a-Chip Technology. IEEE Commun. Magazine 38(12), 70–77 (2000)CrossRefGoogle Scholar
  7. 7.
    Motoyama, S., Santos, C.R.: A Combined Input-Output Queuing ATM Switch With m Internal Links for Cell Transfer. In: International Telecommunications Symposium, September 2002, pp. 142–146 (2002)Google Scholar
  8. 8.
    Motoyama, S., Santos, C.R.: Performance Analysis of a CIOQ ATM Switch With m Internal Links for Cell Transfer. In: 10th International Conference on Software, Telecommunications & Computer Networks – SoftCom 2002, November 2002, pp. 636–640 (2002)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • C. R. dos Santos
    • 1
  • S. Motoyama
    • 2
  1. 1.DEE-INATELSanta Rita do SapucaíBrazil
  2. 2.DT-FEEC-UNICAMPCampinasBrazil

Personalised recommendations