Abstract
This paper presents the design and study of various HEC hunt architectures for ATM frame delineation and explores the trade-offs between the data-path (parallelism) and the hardware cost. A bit-serial, 4-bit, 8-bit, 32-bit and a 64-bit HEC hunt circuit has been implemented and analysed in terms of hardware cost, speed, and data throughput rate. The performances of the bit-parallel architectures have been improved by further pipelining the computation circuit. In the case of the 64-bit data-path architecture, the data throughput capability increased by 63% with an area penalty of only 20%. Post layout results are presented for Altera Stratix FPGA technology.
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Toal, C., Sezer, S. (2004). The Implementation of Scalable ATM Frame Delineation Circuits. In: de Souza, J.N., Dini, P., Lorenz, P. (eds) Telecommunications and Networking - ICT 2004. ICT 2004. Lecture Notes in Computer Science, vol 3124. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-27824-5_137
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DOI: https://doi.org/10.1007/978-3-540-27824-5_137
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22571-3
Online ISBN: 978-3-540-27824-5
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