Advertisement

Intermediate Level Components for Reconfigurable Platforms

  • Erwan Fabiani
  • Christophe Gouyen
  • Bernard Pottier
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)

Abstract

Development productivity is a central point for the acceptance of reconfigurable platforms. Due to the availability of generic low level tools and powerful logic synthesis tools, it becomes possible to define portable components that have both a high level behavior and attributes for physical synthesis. The behavior of a component can be fixed at compile time using concise specifications that will reduce the cost and delays in developments. The method allowing to produce components is illustrated with two case studies.

Keywords

Virtual Machine Cellular Automaton Cellular Automaton Systolic Array Logic Synthesis 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Lagadec, L.: Abstraction, modélisation et outils de CAO pour les circuits intégrés reconfigurables. PhD thesis, Université de Rennes 1 (2000)Google Scholar
  2. 2.
    Cong, J., Ding, Y.: Combinational logic synthesis for lut based fpga. ACM transaction on DAES (1996)Google Scholar
  3. 3.
    Lagadec, L., Pottier, B., Villellas-Guillen, O.: An lut-based high level synthesis framework for reconfigurable architectures. In: Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation, Marcel Dekker (2003)Google Scholar
  4. 4.
    Nicoud, J.D., Tyrrell, A.M.: The transputer t414 instruction set. IEEE Micro  9 (1989)Google Scholar
  5. 5.
    Spinellis, D.: Reliable software implementation using domain specific languages. In: ESREL, 10th european conference on safety and reliability (1999)Google Scholar
  6. 6.
    Dhaussy, P., Filloque, J.M., Pottier, B., Rubini, S.: Global Control Synthesis for an MIMD/FPGA Machine. In: FPGAs for Custom Computing Machines (1994)Google Scholar
  7. 7.
    Bouazza, K., Champeau, J., Ng, P., Pottier, B., Rubini, S.: Implementing cellular automata on the ArMen machine. In: Algorithms and Parallel VLSI Architectures II, Elseiver, Amsterdam (1991)Google Scholar
  8. 8.
    Wu, S., Manber, U.: Fast text searching allowing errors. Communications of the ACM 35 (1992)Google Scholar
  9. 9.
    Champeau, J., Le Pape, L., Pottier, B.: Parallel Grep. In: Algorithms and Parallel VLSI Architectures III, Elsevier, Leuven (1994)Google Scholar
  10. 10.
    Fabiani, E., Lavenier, D.: Experimental evaluation of place-and-route of regular arrays on xilinx chips. In: First International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, USA (2001)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Erwan Fabiani
    • 1
  • Christophe Gouyen
    • 1
  • Bernard Pottier
    • 1
  1. 1.Architectures et SystèmesUniversité de Bretagne OccidentaleBrestFrance

Personalised recommendations