Early ISS Integration into Network-on-Chip Designs

  • Andreas Wieferink
  • Malte Doerper
  • Tim Kogel
  • Rainer Leupers
  • Gerd Ascheid
  • Heinrich Meyr
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)


Future signal processing SoC designs will contain an increasing number of heterogeneous programmable units combined with a complex communication architecture to meet flexibility, performance and cost constraints. Designing such a heterogeneous MP-SoC architecture bears enormous potential for optimization, but requires a system-level design environment and methodology to evaluate architectural alternatives effectively.

Recently, efficient tool frameworks have been proposed to support the design space exploration for large scale embedded systems. The technique presented in this paper allows integrating retargeteable Instruction Set Simulators (ISS) into such an exploration framework very early in the design flow.

In a dual-processor JPEG decoding case study, we illustrate the effectiveness of this approach.


Abstraction Level Data Cache Cache Line Very Large Scale Integration Inverse Discrete Cosine Transformation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Andreas Wieferink
    • 1
  • Malte Doerper
    • 1
  • Tim Kogel
    • 2
  • Rainer Leupers
    • 1
  • Gerd Ascheid
    • 1
  • Heinrich Meyr
    • 1
  1. 1.Institute for Integrated Signal Processing SystemsAachen University of TechnologyGermany
  2. 2.CoWare, Inc 

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