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Initial Evaluation of Multimedia Extensions on VLIW Architectures

  • Esther Salamí
  • Mateo Valero
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)

Abstract

Media processing has motivated strong changes in the focus and design of processors. The inclusion of μSIMD multimedia extensions such as MMX is a cost effective option to improve the performance of those regions of the program with large amounts of DLP. This paper provides an initial evaluation of μSIMD and vector-SIMD enhanced VLIW architectures. We show that these two architectures execute respectively an average of 40% and 57% fewer operations than the reference VLIW architecture. However, when most of the available DLP parallelism has been exploited via multimedia extensions or wide-issue static scheduling, the remaining of the program exhibits only modest amounts of ILP (1.40 operations per cycle for a 8-issue width architecture). We claim that, in general, vector-SIMD extensions achieve the highest speed-ups while still reducing the fetch pressure, although for wide-issue μSIMD architectures reach a similar performance at a lower cost.

Keywords

Very Long Instruction Word Instruction Cache Instruction Word Instruction Level Parallelism Vector Region 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Schlansker, M., Rau, B.R., Mahlke, S., Kathail, V.: Achieving high levels of instruction-level parallelism with reduced hardware complexity. Technical Report HPL-96-120, Hewlett–Packard Laboratories (1994)Google Scholar
  2. 2.
    Johnson, M.: Superscalar Microprocessor Design. Prentice-Hall, Englewood Cliffs (1991)Google Scholar
  3. 3.
    Schlansker, M.S., Raw, B.: Epic: Explicitly parallel instruction computing. IEEE Computer, 37–45 (2000)Google Scholar
  4. 4.
    Intel: Pentium iii processor: Developer’s manual. Technical report, INTEL (1999)Google Scholar
  5. 5.
    Nguyen, H., John, L.K.: Exploiting SIMD parallelism in DSP and multimedia algorithms using the altivec technology. In: International Conference on Supercomputing, pp.11–20 (1999)Google Scholar
  6. 6.
    Corbal, J.: N-Dimensional Vector Instruction Set Architectures for Multimedia Applications. PhD thesis, UPC, Departament d’Arquitectura de Computadors (2002)Google Scholar
  7. 7.
    Salamí, E., Corbal, J., Espasa, R., Valero, M.: An evaluation of different dlp alternatives for the embedded media domain. In: 1st Workshop on Media Processors and DSPs (1999)Google Scholar
  8. 8.
    Corbal, J., Espasa, R., Valero, M.: Exploiting a new level of dlp in multimedia applications. In: 32nd international symposium on Microarchitecture, pp.72– 79 (1999)Google Scholar
  9. 9.
    Mips, S.I.G.: extension for digital media with 3d. Technical report, MIPS Technologies, Inc. (1997)Google Scholar
  10. 10.
    Quintana, F., Corbal, J., Espasa, R., Valero, M.: Adding a vector unit on a superscalar processor. In: International Conference on Supercomputing, pp.1–10 (1999)Google Scholar
  11. 11.
    Lab., H.P., Group, R.I., Group, I.: Trimaran user manual (1998), http://www.trimaran.org/docs.html
  12. 12.
    Kathail, V., Schlansker, M., Rau, B.R.: Hpl-pd architecture specification: Version 1.1. Technical Report HPL-93-80(R.1), Hewlett–Packard Laboratories (2000)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Esther Salamí
    • 1
  • Mateo Valero
    • 1
  1. 1.Computer Architecture DepartmentUPCBarcelona

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