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International Workshop on Embedded Computer Systems

SAMOS 2004: Computer Systems: Architectures, Modeling, and Simulation pp 383–392Cite as

Scalable Instruction-Level Parallelism

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 3133))

Abstract

This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves as a replacement for out-of-order instruction issue; it defines the model and explores implementations issues. The model results in a fully distributed implementation in which data is distributed to one register file per processor, which is scalable as the number of ports in each register file is constant. The only component with less than ideal scaling properties is the the switching network between processors.

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References

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Author information

Authors and Affiliations

  1. Department of Computer Science, University of Amsterdam, Kruislaan 403, 1098 SJ, Amsterdam, The Netherlands

    Chris Jesshope

Authors
  1. Chris Jesshope
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Editor information

Editors and Affiliations

  1. Computer Systems Architecture Group, University of Amsterdam, The Netherlands

    Andy D. Pimentel

  2. Computer Engineering Lab, TUDelft., Postbus 5031, 2600 GA, Delft, The Netherlands

    Stamatis Vassiliadis

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© 2004 Springer-Verlag Berlin Heidelberg

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Jesshope, C. (2004). Scalable Instruction-Level Parallelism. In: Pimentel, A.D., Vassiliadis, S. (eds) Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2004. Lecture Notes in Computer Science, vol 3133. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-27776-7_40

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  • DOI: https://doi.org/10.1007/978-3-540-27776-7_40

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-22377-1

  • Online ISBN: 978-3-540-27776-7

  • eBook Packages: Springer Book Archive

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