Scalable Instruction-Level Parallelism

  • Chris Jesshope
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)


This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves as a replacement for out-of-order instruction issue; it defines the model and explores implementations issues. The model results in a fully distributed implementation in which data is distributed to one register file per processor, which is scalable as the number of ports in each register file is constant. The only component with less than ideal scaling properties is the the switching network between processors.


Switching Network Dependency Distance Instruction Issue Main Thread Issue Width 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Chris Jesshope
    • 1
  1. 1.Department of Computer ScienceUniversity of AmsterdamAmsterdamThe Netherlands

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