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Scalable FFT Processors and Pipelined Butterfly Units

  • Jarmo Takala
  • Konsta Punkka
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)

Abstract

This paper considers partial-column radix-2 FFT processors. The efficiency of processors based on bit-parallel multipliers, distributed arithmetic, and CORDIC is analyzed with the aid of logic synthesis.

Keywords

Fast Fourier Transform Fast Fourier Transform Algorithm CORDIC Algorithm Clock Constraint Twiddle Factor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Jarmo Takala
    • 1
  • Konsta Punkka
    • 1
  1. 1.Tampere University of TechnologyTampereFinland

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