Dynamic Hardware Reconfigurations: Performance Impact for MPEG2

  • Elena Moscu Panainte
  • Koen Bertels
  • Stamatis Vassiliadis
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)


In this paper, we study the impact dynamic reconfiguration has on the performance of current reconfigurable technology. As a testbed, we use the Xilinx Virtex II Pro, the Molen experimental platform and the MPEG2 encoder as the application. We show for the MPEG2 encoder that a substantial overall performance improvement, up to 34 %, can be achieved when SAD, DCT and IDCT functions are executed on the reconfigurable hardware when the compiler anticipates and separates configuration from execution. This study also considers the impact inappropriate scheduling can have on the overall performance. We show that slowdowns of up to a factor 1000 are observed when the configuration latency is not hidden by the compiler. Our experiments show that appropriate scheduling allows to exploit up to 97% of the maximal theoretical speedup.


Field Programmable Gate Array General Purpose Processor Hardware Acceleration MPEG2 Encoder Execute Instruction 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Elena Moscu Panainte
    • 1
  • Koen Bertels
    • 1
  • Stamatis Vassiliadis
    • 1
  1. 1.Computer Engineering LabDelft University of TechnologyThe Netherlands

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