Embedded Context Aware Hardware Component Generation for Dataflow System Exploration

  • John Mc Allister
  • Roger Woods
  • Richard Walke
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)


Techniques for the rapid deployment and architectural exploration of complex digital signal processing algorithms on embedded processor platforms are gaining popularity. These become significantly more complicated when dedicated hardware components need to be integrated. The models on which such design methodologies and tools are based highlight the system level inflexibility with both pre-designed intellectual property cores and most customized component creation techniques. This paper presents a technique for overcoming these deficiencies using a dataflow model of computation, by allowing flexible circuit architectures to be created that can be optimized as desired, providing increased throughput with no extra resource usage in some situations.


Input Stream Packet Switch Signal Flow Graph Dataflow Model Synchronous Data Flow 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • John Mc Allister
    • 1
  • Roger Woods
    • 1
  • Richard Walke
    • 2
  1. 1.Institute for Electronic, Communication and Information Technology (ECIT)Queens University BelfastBelfastUK
  2. 2.Real Time Embedded Systems (RTES), QinetiQ Ltd.Great Malvern, WorcestershireUK

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