Abstract
Loop unrolling plays an important role in compilation for Reconfigurable Processing Units (RPUs) as it exposes operator parallelism and enables other transformations (e.g., scalar replacement). Deciding when and where to apply loop unrolling, either fully or partially, leads to large design space exploration problems. In order to cope with these vast spaces, researchers have explored the application of design estimation techniques. Using estimation, tools can conduct early evaluation of the impact and interplay of transformations in both the required resources and expected performance. In this paper we present some of the current approaches and issues related to estimation of the loop unrolling impact when targeting RPUs.
This work is partially supported by the Portuguese Foundation for Science and Technology (FCT) – FEDER and POSI programs – under the CHIADO project. João Cardoso gratefully acknowledges the donation by PACT XPP Technologies, Inc, of the XPP development suite (XDS) software.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Böhm, W., et al.: Mapping a Single Assignment Programming Language to Reconfigurable Systems. The Journal of Supercomputing 21(2), 117–130 (2002)
Triantafyllis, S., et al.: Compiler Optimization-Space Exploration. In: Proc. of Int’l Symposium on Code Generation and Optimization (CGO 2003), San Francisco, CA, USA (2003)
So, B., Hall, M., Diniz, P.: A Compiler Approach to Fast Hardware Design Space Exploration for FPGA Systems. In: Proc. of ACM Conference on Programming Language Design and Implementation (PLDI 2002), Berlin, Germany, June 17-19 (2002)
So, B., Diniz, P., Hall, M.: Using Estimates from Behavioral Synthesis Tools in Compiler- Directed Design Space Exploration. In: Proc. of Design Automation Conference (DAC 2003) (June 2003)
PACT XPP Technologies, Inc.:The XPP White Paper .Release 2.1.1 (March 2002)
Cardoso, J., Diniz, P., Weinhardt, M.: Compilation for Reconfigurable Computing Platforms: Comments on Techniques and Current Status. INESC-ID Technical Report, RT/009/ (October 2003)
Gokhale, M., Stone, J.M., Gomersall, E.: Co-synthesis to a hybrid RISC/FPGA architecture. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology 24(2), 165–180 (2000)
Annapolis Micro Systems Inc.: WildStar Reconfigurable Computing Engines. User’s Manual R3.3 (1999)
Goldstein, S., et al.: PipeRench: A Reconfigurable Architecture and Compiler. IEEE Computer 33(4), 70–77 (2000)
Wolfe, M.: High Performance Compilers for Parallel Computing. Addison-Wesley, Reading (1996)
Cardoso, J., Weinhardt, M.: XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 864–874. Springer, Heidelberg (2002)
Nayak, A., et al.: Accurate Area and Delay Estimators for FPGAs. In: Proc. Design Automation and Test in Europe (DATE 2002), Paris, France, March 2002,pp. 862-869 (2002)
Park, J., Diniz, P., Raghunathan, S.: Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, Springer, Heidelberg (2003)
Koseki, A., Komatsu, H., Fukazawa, Y.: A Method for Estimating Optimal Unrolling Times for Nested Loops. In: Proc. of Int’l Symposium on Parallel Architectures, Algorithms and Networks (ISPAN 1997), Taipei, Taiwan, pp. 376–382. IEEE CS Press, Los Alamitos (1997)
Zhao, M., Childers, B.R., Soffa, M.L.: Predicting the impact of optimizations for embedded systems. In: ACM SIGPLAN Symposium on Languages, Compilers, and Tools for Embedded Systems (LCTES 2003), San Diego, CA, USA (June 2003)
Liao, J., Wong, W.F., Tulika, M.: A Model for Hardware Realization of Kernel Loops. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 334–344. Springer, Heidelberg (2003)
Cardoso, J.: Loop Dissevering: A Technique for Temporally Partitioning Loops in Dynamically Reconfigurable Computing Platforms. In: Proc. of Reconfigurable Architecturesc Workshop (RAW 2003), Nice, France (April 2003)
So, B., Hall, M.: Increasing the Applicability of Scalar Replacement. In: Proc. of Int’l Conference on Compiler Construction (CC 2004), ACM Press, New York (2004)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Cardoso, J.M.P., Diniz, P.C. (2004). Modeling Loop Unrolling: Approaches and Open Issues. In: Pimentel, A.D., Vassiliadis, S. (eds) Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2004. Lecture Notes in Computer Science, vol 3133. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-27776-7_24
Download citation
DOI: https://doi.org/10.1007/978-3-540-27776-7_24
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22377-1
Online ISBN: 978-3-540-27776-7
eBook Packages: Springer Book Archive