Abstract
We use the Xilinx Virtex II ProTM technology as prototyping platform to design a MOLEN polymorphic processor, a custom computing machine based on the co-processor architectural paradigm. The PowerPC embedded in the FPGA is operating as a general purpose (core) processor and the reconfigurable fabric is used as a reconfigurable co-processor. The paper focuses on hardware synthesis results and experimental performance evaluation, proving the viability of the MOLEN concept. More precisely, the MPEG-2 application is accelerated very closely to its theoretical limits by implementing SAD, DCT and IDCT as reconfigurable co-processors. For a set of popular test video sequences the MPEG-2 encoder overall speedup is in the range between 2.64 and 3.18. The speedup of the MPEG-2 decoder varies between 1.65 and 1.94.
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References
Campi, F., Toma, M., Lodi, A., Cappelli, A., Canegallo, R., Guerrieri, R.: VLIW Processor with Reconfigurable Instruction Set for Embedded Applications. In: ISSCC Digest of Technical Papers, February 2003, pp. 250–251 (2003)
Gokhale, M., Stone, J.: Napa C: Compiling for a Hybrid RISC/FPGA Architecture. In: Proc. IEEE Symp. on FCCM, pp. 126–135 (1998)
Hauck, S., Fry, T., Hosler, M., Kao, J.: The Chimaera Reconfigurable Functional Unit. In: Proc. IEEE Symp. on FCCM, pp. 87–96 (1997)
Kuzmanov, G., Gaydadjiev, G.N., Vassiliadis, S.: Loading rm-code: Design considerations. In: Proc. Third Intl. Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2003), pp. 8–11 (2003)
Kuzmanov, G., Vassiliadis, S.: Arbitrating Instructions in an ρμ-coded CCM. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 81–90. Springer, Heidelberg (2003)
Rosa, L., Lavagno, L., Passerone, C.: Hardware/Software Design Space Exploration for a Reconfigurable Processor. In: Proc. DATE 2003, pp. 570–575 (2003)
Vassiliadis, S., Gaydadjiev, G.N., Bertels, K., Panainte, E.M.: The molen programming paradigm. In: Proc. Third Intl.Workshop on Systems, Architectures,Modeling, and Simulation (SAMOS 2003) , pp. 1–7 (2003)
Vassiliadis, S., Hakkennes, E., Wong, S., Pechanek, G.: The Sum-of-Absolute-Difference Motion Estimation Accelerator. In: Proc. 24th Euromicro Conf., pp. 559–566 (1998)
Vassiliadis, S., Wong, S., Cotofana, S.: The MOLEN ρμ-coded processor. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol. 2147, pp. 275–285. Springer, Heidelberg (2001)
Xilinx Corporation. Virtex-II Pro Platform FPGA Handbook, v.1.0 (2002)
Ye, A., Shenoy, N., Banerjee, P.: A C Compiler for a Processor with a Reconfigurable Functional Unit. In: ACM/SIGDA Symp. on FPGAs, pp. 95–100 (2000)
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Kuzmanov, G., Gaydadjiev, G., Vassiliadis, S. (2004). The Virtex II ProTM MOLEN Processor. In: Pimentel, A.D., Vassiliadis, S. (eds) Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2004. Lecture Notes in Computer Science, vol 3133. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-27776-7_21
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DOI: https://doi.org/10.1007/978-3-540-27776-7_21
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