Loading ρμ-Code: Design Considerations

  • Georgi Kuzmanov
  • Georgi Gaydadjiev
  • Stamatis Vassiliadis
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)


This article investigates microcode generation, finalization and loading in MOLEN ρμ processors. In addition, general solutions for these issues are presented and implementation for Xilinx Virtex-II Pro platform FPGA is introduced.


Reconfigurable architectures MOLEN implementation loading microcode 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Georgi Kuzmanov
    • 1
  • Georgi Gaydadjiev
    • 1
  • Stamatis Vassiliadis
    • 1
  1. 1.Computer Engineering Laboratory, Electrical Engineering Dept., EEMCSTU DelftThe Netherlands

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